Hierarchical Design Guidelines

Incremental Design takes advantage of design hierarchy to limit changes to smaller portions of the design. In addition to partitioning the design into separate logic groups with “Incremental Synthesis,” it is also important that the design follow good hierarchical design methodologies. The MAP and PAR implementation tools prevent logic optimizations across logic group boundaries when logic groups are defined on hierarchical boundaries in the design. The following are guidelines for creating good hierarchical designs:

The design should be fully synchronous.
The top level of the design should only contain instantiated logic groups, IOB logic, and clock logic (DCMs, BUFGs, etc.). Since area for top level logic is generally not reserved, this prevents changing top level logic placed within AREA GROUP RANGEs from causing changes in unchanged logic groups.
Registers should be placed on all of the outputs of each logic group. This will ensure that the critical paths are contained inside of a logic group and eliminate possible problems with logic optimization across logic group boundaries.
The timing constraints on the design should be realistic and should be attainable when processing the design without using Incremental Design.

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