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Modular Design Entry and Synthesis
The team leader creates the top-level design using an HDL and synthesizes this design. The top-level design includes all global logic, including I/Os, all modules instantiated as “black boxes” with only ports and port directions, and the signals that connect modules to each other and to I/O ports. This step must occur before Modular Design Implementation can begin.
The team members create individual module designs using an HDL and synthesize the designs. However, this does not need to occur before the Modular Design Implementation step begins. Team members can work on their module designs while the team leader moves on to the Initial Budgeting phase of Modular Design Implementation. Team members must complete design entry and synthesis for their modules prior to the Active Module Implementation phase of Modular Design Implementation.
You can enter your design with a text-based tool using Verilog or VHDL. To synthesize your design, you can use Xilinx-supported third-party tools, which produce a design file in third-party netlist formats, or you can use the Xilinx synthesis tool, Xilinx Synthesis Technology (XST), that produces a netlist in NGC format. For more information on XST, see the Synthesis and Verification Design Guide.
As with standard design entry, Modular Design entry begins with a design concept, expressed as a functional description. From the original design, a netlist is created. For details on HDL design entry, see "HDL Entry and Synthesis" in Chapter 2. Also, see the Synthesis and Verification Design Guide.
The following figure shows the Modular Design entry and synthesis flow.
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