Modular Design Troubleshooting

Following are troubleshooting tips for working with Modular Design. For additional troubleshooting help, use the resources at http://www.xilinx.com/support.

Multiple Output Ports MAP Error

If you include a signal in a module that drives more than one output port, the tools attempt to replicate this signal, and its driving logic such that distinct identical signals are used for each output port. This replication is needed to maintain the permanence of the defined module boundary against signal collapse. This type of replication can be noted by Warnings in the MAP report file. If this automatic replication is unacceptable for your design, then you should manually address this problem in your HDL code for the module.

Part Type Specification

If you are targeting a part different from the one specified in your source design, you must specify the exact same part type using the -p option every time you run NGDBuild. The syntax for the –p option is described in "–p (Part Number)" in Chapter 1. Failure to adhere to this generates modules with different part types that cannot be assembled into a final design.

Constraints Not Working in Active Module Implementation

If it appears that a constraint is not being processed, make sure there are not multiple versions of the same constraint defined in the NCF or UCF file. In most cases, if a constraint is defined multiple times, the last definition of the constraint overwrites any previous definitions. To specify more than one value for a particular constraint, list all the values on the same line.

Correct

The following syntax reserves both site “PAD43” and site “PAD21” for the module named “A”:

MODULE A RESERVED_SITES = “PAD43, PAD21”;

Incorrect

In the following syntax, the second RESERVED_SITE constraint overwrites the first, and the site “PAD43” is not reserved:

MODULE A RESERVED_SITES = “PAD43”;

MODULE A RESERVED_SITES = “PAD21”;

Resource Contention or Timing Constraints Not Met in Final Assembly

Resource contention among modules can occur due to module use of global logic or routing resources. Also, even if each module meets its timing constraints, the overall design may not meet its timing constraints due to additive delays. If either of these conditions occur, reimplement one or more modules as described in "Implementing an Active Module" before proceeding to the Final Assembly phase.

Note: Although it is possible to use tools during the Final Assembly phase to directly manipulate resources contained in a module, this is not recommended, because it renders published module information invalid for future iterations.