Vendor Specific Notes for Synthesis

Vendor Specific Notes for Synthesis

Use the following procedures for your particular synthesis tool. If your tool is not listed, refer to your tool’s user documentation.

Synplify

Use the following procedures if you are synthesizing with Synplify:

Creating a Netlist for Each Module (Synplify)

Each design project creates one netlist. To create a netlist for each module, do the following:

Create a project for the top-level design and for each lower-level module.

Synthesize the top-level project with I/O insertion and the
lower-level modules without I/O insertion.

Disabling I/O Insertion for a Module (Synplify)

To disable I/O insertion for a module, do the following:

Select Target Set Device Options.

In the Set Device Options dialog box, select Disable I/O Insertion.

Disabling I/O Insertion for a Module (Synplify Pro)

To disable I/O insertion for a module, do the following:

Select Impl Options

In the Options for Implementation dialog box, select the box next to Disable I/O insertions in the Device Mapping Option portion of the dialog box.

Instantiating Primitives (Synplify and Synplify Pro)

For both VHDL and Verilog, you do not need to declare modules when calling primitives and mapping ports. Synplify provides Virtex primitives in the following areas:

VHDL: “library architecture” located in $SYNPLICITY/lib/xilinx

Verilog: and “architecture.v” located in $SYNPLICITY/lib/xilinx

LeonardoSpectrum

Use the following procedures if you are synthesizing with LeonardoSpectrum.

Creating a Netlist for Each Module (LeonardoSpectrum)

To create a netlist for each module, you can create multiple netlists from a single project using the GUI or using a script.

Following is a script example for a VHDL design:

set part v50ecs144

load_library xcve

read ./top.vhd

optimize -target xcve -hier preserve

present_design .work.top.modular

auto_write -format edf top.edf

read ./module_a.vhd

read ./module_b.vhd

read ./module_c.vhd

optimize -target xcve -hier preserve

present_design .work.module_a.modular

auto_write -format edf module_a.edf

present_design .work.module_b.modular

auto_write -format edf module_b.edf

present_design .work.module_c.modular

auto_write -format edf module_c.edf

Following is a script example for a Verilog design:

set part v50ecs144

load_library xcve

read ./module_a.v

read ./module_b.v

read ./module_c.v

read ./top.v

optimize -target xcve -hier preserve

present_design .work.module_a.INTERFACE

auto_write -format edf module_a.edf

present_design .work.module_b.INTERFACE

auto_write -format edf module_b.edf

present_design .work.module_c.INTERFACE

auto_write -format edf module_c.edf

NOOPT .work.module_a.INTERFACE

NOOPT .work.module_b.INTERFACE

NOOPT .work.module_c.INTERFACE

present_design .work.top.INTERFACE

auto_write -format edf top.edf

Disabling I/O Insertion for a Module (LeonardoSpectrum)

To disable I/O insertion for a module, do the following:

Select the Quick Setup tab.

Make sure the Insert I/O Pads checkbox is deselected.

Instantiating Primitives (LeonardoSpectrum)

Instantiating primitives differs based on whether you use VHDL or Verilog.

VHDL: You must declare all instantiated components in the code.

Verilog: You do not need to declare modules in the code.

XST

Creating a Netlist for Each Module (XST)

Use the Incremental Synthesis feature to synthesize each design module individually within a project. To create a netlist for each module, do the following:

In the Project Navigator, select your module design in the Source window.

Select Synthesize in the Process window.

Select ProcessProperties.

Export the design to produce a separate NGC file for each module.

Disabling I/O Insertion for a Module (XST)

To disable I/O insertion for a module, do the following:

In the Xilinx Project Navigator, select your module design in the Source window.

Select Synthesize in the Process window.

Select ProcessProperties.

In the Xilinx Specific Options tab of the Process Properties dialog box, make sure the Add I/O Buffers checkbox is deselected.

Instantiating Primitives (XST)

XST instantiates primitives automatically.