HDL Code Examples

HDL Code Examples

Following are code examples for your reference.

Top-Level Design

The top-level design should include all global logic, all design modules, and the logic that connects modules to each other and to
I/O ports. Each module should be instantiated as a “black box,” with only ports and port directions. For general coding guidelines, see "General Coding Guidelines".

VHDL Example: Top-Level Design

library IEEE;

use IEEE.std_logic_1164.all;

entity top is port (ipad_dll_clk_in: in std_logic;

    dll_rst : in std_logic;

    top2a_c: in std_logic;

    top2b: in std_logic;

    obuft_out: out std_logic;

    mod_c_out: out std_logic;

    moda_clk_pad: in std_logic;

    moda_data: in std_logic;

    moda_out: out std_logic;

    modb_clk_pad: in std_logic;

    modb_data: in std_logic;

    modb_out: out std_logic;

    modc_clk_pad: in std_logic;

    modc_data: in std_logic;

    modc_out: out std_logic

) ;

end top;

architecture modular of top is

signal dll_clk_in : std_logic;

signal clk_top : std_logic;

signal dll_clk_out: std_logic;

signal a2top_obuft_i: std_logic;

signal a2c: std_logic;

signal a2b: std_logic;

signal b2top_obuft_t: std_logic;

signal b2c: std_logic;

signal b2a: std_logic;

signal c2and2: std_logic;

signal c2a: std_logic;

signal a_and_c: std_logic;

signal moda_clk: std_logic;

signal modb_clk: std_logic;

signal modc_clk: std_logic;

component IBUFG is port
( I : in std_logic;

O : out std_logic);

end component;

component CLKDLL is port (

  CLKIN : in std_logic;

  CLKFB : in std_logic;

  RST : in std_logic;

  CLK0 : out std_logic;

  CLK90 : out std_logic;

  CLK180 : out std_logic;

  CLK270 : out std_logic;

  CLKDV : out std_logic;

  CLK2X : out std_logic;

  LOCKED : out std_logic);

  end component;



component BUFG is port

  I : in std_logic;

  O : out std_logic);

  end component;

component BUFGP

  port (

  I : in std_logic;

  O : out std_logic);

  end component;

-- Declare modules at top-level to get port directionality

component module_a is port( CLK_TOP: in std_logic;

    B2A_IN: in std_logic;

    TOP2A_IN: in std_logic;

    C2A_IN: in std_logic;

    MODA_DATA : in std_logic;

    MODA_CLK : in std_logic;

    A2B_OUT: out std_logic;

    A2TOP_OBUFT_I_OUT: out std_logic;

    A2c_ouT: out std_logic;

    MODA_OUT : out std_logic

);

end component;

component module_b is port( CLK_TOP: in std_logic;

    A2B_IN: in std_logic;

    TOP2B_IN: in std_logic;

    A_AND_C_IN: in std_logic;

    MODB_DATA: in std_logic;

    MODB_CLK: in std_logic;

    MODB_OUT : out std_logic;

    B2A_OUT: out std_logic;

    B2TOP_OBUFT_T_OUT: out std_logic;

    B2C_OUT: out std_logic);

end component;

component module_c is port( CLK_TOP: in std_logic;

    B2C_IN: in std_logic;

    TOP2A_C_IN: in std_logic;

    A2C_IN: in std_logic;

    MODC_DATA: in std_logic;

    MODC_CLK: in std_logic;

    MODC_OUT: out std_logic;

    C2A_OUT: out std_logic;

    C2TOP_OUT: out std_logic;

    C2AND2_OUT: out std_logic);

end component;

begin

ibuf_dll: IBUFG port map(I =>ipad_dll_clk_in,

    O => dll_clk_in);

dll_1: CLKDLL port map(CLKIN => dll_clk_in,

    CLKFB => clk_top,

    CLK0 => dll_clk_out,

    RST => dll_rst);

globalclk: BUFG port map(O => clk_top,

    I => dll_clk_out);

bufg_moda : BUFGP port map (O => moda_clk,

    I => moda_clk_pad);

bufg_modb : BUFGP port map (O => modb_clk,

    I => modb_clk_pad);

bufg_modc : BUFGP port map ( O => modc_clk,

    I => modc_clk_pad);

-- A simple piece of external logic at top level

a_and_c <= c2and2 and b2a;

-- Tri-state output

obuft_out <= a2top_obuft_i when b2top_obuft_t = ’0’ else ’Z’;

instance_a: module_a port map (CLK_TOP =>clk_top,

    TOP2A_IN =>top2a_c,

    C2A_IN =>c2a,

    B2A_IN => b2a,

    MODA_DATA => moda_data,

    MODA_CLK => moda_clk,

    MODA_OUT => moda_out,

    A2B_OUT => a2b,

    A2TOP_OBUFT_I_OUT => a2top_obuft_i,

    A2C_OUT => a2c) ;

instance_b: module_b port map ( CLK_TOP => clk_top,

    TOP2B_IN => top2b,

    A2B_IN => a2b,

    A_AND_C_IN => a_and_c,

    MODB_DATA => modb_data,

    MODB_CLK => modb_clk,

    MODB_OUT => modb_out,

    B2TOP_OBUFT_T_OUT => b2top_obuft_t,

    B2C_OUT => b2c,

    B2A_OUT => b2a);

instance_c: module_c port map ( CLK_TOP => clk_top,

    TOP2A_C_IN => top2a_c,

    B2C_IN => b2c,

    A2C_IN => a2c,

    MODC_DATA => modc_data,

    MODC_CLK => modc_clk,

    MODC_OUT => modc_out,

    C2TOP_OUT => mod_c_out,

    C2AND2_OUT => c2and2,

    C2A_OUT => c2a);

end modular;

Verilog Example: Top-Level Design

module top (ipad_dll_clk_in, dll_rst, top2a_c, top2b, obuft_out,

mod_c_out, moda_data, moda_clk_pad, moda_out, modb_data,

modb_clk_pad, modb_out, modc_data, modc_clk_pad, modc_out) ;

  input ipad_dll_clk_in;

  input dll_rst;

  input top2a_c;

  input top2b;

  output obuft_out;

  output mod_c_out;

  input moda_data;

  input moda_clk_pad;

  output moda_out;

  input modb_data;

  input modb_clk_pad;

  output modb_out;

  input modc_data;

  input modc_clk_pad;

  output modc_out;

//wire ipad_dll_clk_out;

  wire clk_top;

  wire dll_clk_out;

  wire a2top_obuft_i;

  wire a2c;

  wire a2b;

  wire b2top_obuft_t;

  wire b2c;

  wire b2a;

  wire c2and2;

  wire c2a;

  wire a_and_c;

  wire moda_clk;

  wire modb_clk;

  wire modc_clk;

IBUFG ibuf_dll (.I(ipad_dll_clk_in),

    .O(dll_clk_in));

CLKDLL dll_1 (.CLKIN(dll_clk_in),

    .CLKFB(clk_top),

    .CLK0(dll_clk_out),

    .RST(dll_rst));

BUFG globalclk (.O(clk_top),

    .I(dll_clk_out));

BUFGP bufg_moda (.O(moda_clk),

    .I(moda_clk_pad));

BUFGP bufg_modb (.O(modb_clk),

    .I(modb_clk_pad));

BUFGP bufg_modc (.O(modc_clk),

    .I(modc_clk_pad));

// A simple piece of external logic at top level

assign a_and_c = c2and2 && b2a;

// Tri-state output

assign obuft_out = (!b2top_obuft_t) ? a2top_obuft_i : 1’bz;

module_a instance_a (.CLK_TOP(clk_top),

    .B2A_IN(b2a),

    .TOP2A_IN(top2a_c),

    .C2A_IN(c2a),

    .MODA_DATA(moda_data),

    .MODA_CLK (moda_clk),

    .MODA_OUT (moda_out),

    .A2B_OUT(a2b),

    .A2TOP_OBUFT_I_OUT(a2top_obuft_i),

    .A2C_OUT(a2c)) ;

module_b instance_b ( .CLK_TOP(clk_top),

    .TOP2B_IN(top2b),

    .A2B_IN(a2b),

    .A_AND_C_IN(a_and_c),

    .MODB_DATA(modb_data),

    .MODB_CLK(modb_clk),

    .MODB_OUT(modb_out),

    .B2TOP_OBUFT_T_OUT(b2top_obuft_t),

    .B2C_OUT(b2c),

    .B2A_OUT(b2a));

module_c instance_c ( .CLK_TOP(clk_top),

    .TOP2A_C_IN(top2a_c),

    .B2C_IN(b2c),

    .A2C_IN(a2c),

    .MODC_DATA(modc_data),

    .MODC_CLK(modc_clk),

    .MODC_OUT(modc_out),

    .C2TOP_OUT(mod_c_out),

    .C2AND2_OUT(c2and2),

    .C2A_OUT(c2a));

endmodule

// Declare modules at top-level to get port directionality

module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA,

MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT) ;

  input CLK_TOP ;

  input B2A_IN ;

  input TOP2A_IN ;

  input C2A_IN ;

  input MODA_DATA;

  input MODA_CLK;

  output MODA_OUT;

  output A2B_OUT ;

  output A2TOP_OBUFT_I_OUT ;

  output A2C_OUT ;

endmodule

module module_b ( CLK_TOP, A2B_IN, TOP2B_IN, A_AND_C_IN, MODB_DATA,

MODB_CLK, MODB_OUT, B2A_OUT, B2TOP_OBUFT_T_OUT, B2C_OUT) ;

  input CLK_TOP ;

  input A2B_IN ;

  input TOP2B_IN ;

  input A_AND_C_IN ;

  input MODB_DATA;

  input MODB_CLK;

  output MODB_OUT;

  output B2A_OUT ;

  output B2TOP_OBUFT_T_OUT ;

  output B2C_OUT ;

endmodule

module module_c ( CLK_TOP, B2C_IN, TOP2A_C_IN, A2C_IN, MODC_DATA,

MODC_CLK, MODC_OUT, C2A_OUT, C2TOP_OUT, C2AND2_OUT) ;

  input CLK_TOP ;

  input B2C_IN ;

  input TOP2A_C_IN ;

  input A2C_IN ;

  input MODC_DATA;

  input MODC_CLK;

  output MODC_OUT;

  output C2A_OUT ;

  output C2TOP_OUT ;

  output C2AND2_OUT ;

endmodule

External I/Os in a Module

It is recommended that you declare external I/Os in the top-level design. However, you can include external I/Os in a module without modifying the top-level code. This may be useful if you want to add a temporary external I/O in the module for simulation. To do this, explicitly instantiate IBUF/IBUFG/BUFGP and OBUF connections. Following are examples of code.

Note: Do not directly connect these I/Os to module ports.

VHDL Example: Module Design with Inserted I/Os

library IEEE;

use IEEE.std_logic_1164.all;

entity module_a is port ( CLK_TOP : in std_logic;

    B2A_IN: in std_logic;

    TOP2A_IN: in std_logic;

    C2A_IN: in std_logic;

    MODA_DATA : in std_logic;

    MODA_CLK : in std_logic;

    MODA_OUT : out std_logic;

    A2B_OUT: out std_logic;

    A2TOP_OBUFT_I_OUT: out std_logic;

    A2C_OUT: out std_logic) ;

end module_a;

architecture modular of module_a is

-- add your signal declarations here

signal Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT : std_logic;

signal AND4_OUT: std_logic ;

signal OR4_OUT : std_logic;

begin

AND4_OUT <= Q0_OUT and Q1_OUT and Q2_OUT and Q3_OUT ;

OR4_OUT <= Q0_OUT or Q1_OUT or Q2_OUT or Q3_OUT ;

TOP_CLK: process(CLK_TOP)

begin

if (CLK_TOP’event and CLK_TOP = ’1’) then

  Q0_OUT <= MODA_DATA ;

  Q2_OUT <= TOP2A_IN ;

  MODA_OUT <= OR4_OUT ;

  A2B_OUT <= AND4_OUT ;

end if;

end process TOP_CLK;

CLK_MODA: process(MODA_CLK)

begin

if (MODA_CLK’event and MODA_CLK = ’1’) then

  Q1_OUT <= B2A_IN ;

  Q3_OUT <= C2A_IN ;

  A2TOP_OBUFT_I_OUT <= AND4_OUT ;

  A2C_OUT <= OR4_OUT ;

end if;

end process CLK_MODA;

end modular;

Verilog Example: Module Design with Inserted I/Os

In the following example, the module has two external inputs (IPAD_MODA_CLK and IPAD_MODA_DATA) and one external output (OPAD_MODA_OUT). These external I/Os, IBUF, OBUF, and BUFGP are instantiated.

The lower-level port declaration is different from the top-level declaration of module_a. Lower-level module_a has three additional ports. With Modular Design, NGDBuild ignores this port mismatch and uses module_a.edf to describe module_a. These
I/Os will be present in the design and available for simulation.

module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA,

MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT);

input CLK_TOP ;

input B2A_IN ;

input TOP2A_IN ;

input C2A_IN ;

input MODA_DATA, MODA_CLK;

output MODA_OUT;

output A2B_OUT ;

output A2TOP_OBUFT_I_OUT ;

output A2C_OUT ;

// add your declarations here

reg Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT ;

reg A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT ;

reg MODA_OUT;

wire AND4_OUT ;

wire OR4_OUT ;

// add your code here

assign AND4_OUT = Q0_OUT && Q1_OUT && Q2_OUT && Q3_OUT ;

assign OR4_OUT = Q0_OUT || Q1_OUT || Q2_OUT || Q3_OUT ;

always @ (posedge CLK_TOP)

begin : TOP_CLK

  Q0_OUT <= MODA_DATA ;

  Q2_OUT <= TOP2A_IN ;

  MODA_OUT <= OR4_OUT ;

  A2B_OUT <= AND4_OUT ;

end

always @ (posedge MODA_CLK)

begin : CLK_MODA

  Q1_OUT <= B2A_IN ;

  Q3_OUT <= C2A_IN ;

  A2TOP_OBUFT_I_OUT <= AND4_OUT ;

  A2C_OUT <= OR4_OUT ;

end

endmodule