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Partial Reconfiguration Overview
An important feature in Xilinx architecture is the ability to reconfigure a portion of an FPGA while the remainder of the design is still operational. Certain areas of a device can be reconfigured while other areas remain operational and unaffected by reprogramming. Partial Reconfiguration is done when the device is active.
Styles of Partial Reconfiguration
There are two main styles of Partial Reconfiguration: Module-based and Difference-based.
Module-Based
Module-based Partial Reconfiguration is used when communication is needed between modules. For modules that communicate with each other, a special bus macro (described in "Bus Macro Communication") allows signals to cross over a Partial Reconfiguration boundary. Without this special consideration, intermodule communication would not be feasible as it is impossible to guarantee routing between modules. The bus macro provides a fixed bus of inter-design communication. Each time Partial Reconfiguration is performed, the bus macro is used to establish unchanging routing channels between modules, guaranteeing correct connections.
The "Module-Based Partial Reconfiguration" flow is used for these designs.
Note: For designs where the modules are completely independent (no common I/O except clocks) and there is no communication between modules, bus macros are not needed.
Difference-Based
This method of Partial Reconfiguration is accomplished by making a small change to a design (normally done in FPGA_Editor), and then by generating a bitstream based on only the differences in the two designs. Switching the configuration of a module from one implementation to another is very quick, as the bitstream differences can be extremely smaller than the entire device bitstream.
The "Difference-Based Partial Reconfiguration" flow is used for these designs.
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