Difference-Based Partial Reconfiguration

Difference-Based Partial Reconfiguration

There are two main ways a design can be altered to be utilized with Difference-based Partial Reconfiguration. The design can change either at the front-end (HDL or Schematic) or the back-end (NCD file). For front-end changes, the design must be re-synthesized and
re-implemented to create a newly placed and routed NCD file. For back-end changes to the NCD files, sections of a design can be modified using the FPGA Editor tool. BitGen switches then can produce custom bitstreams that only modify small sections of the device.

Switching the configuration of a module from one implementation to another is very quick, as the bitstream differences are smaller than the changes to an entire device bitstream. These bitstreams can be loaded quickly and easily due to their size and software support.

In designs where large blocks of logic are meant to be reconfigured, the Modular Design flow described in the "Module-Based Partial Reconfiguration" section is required. However, there are many uses for minute design changes. Perhaps LUT programming or an I/O standard needs to be changed and loaded on the fly. These sorts of changes can be made easily by directly editing the routed NCD file in the Xilinx FPGA Editor application. If BRAM contents need to be modified, the Data2MEM utility can help, or these changes can be made in FPGA Editor as well. Once the changes are made, the BitGen program can be used to produce a bitstream that only programs the differences between the original design and the new one. Depending on the changes made, this partial bitstream can be orders of magnitude smaller than the original. All that is required is a good understanding of how to make logic changes using the FPGA Editor application, and the pertinent options to select in BitGen.

Making Small Design Changes Using FPGA Editor

While there are a myriad of different types of changes that can be made to an FPGA design, this chapter only addresses three of them in FPGA Editor — changing I/O standards, BRAM contents, and LUT programming. While it is possible to change routing information, this is not recommended due to the possibility of internal contention during reconfiguration. If routing changes are desired, using the flow described in this chapter is recommended.

Once the routed NCD file is opened in FPGA Editor (by specifying it on the command line or using the FileOpen menu selection), immediately save it under a different name, so the original design is not lost. The first example in the following figure shows that FileSave As is selected to change the and_test.ncd design to and_test2.ncd. The latter file will remain open in FPGA Editor once the operation is complete.

Once the new design is open, make the file available for modification by selecting FileMain Properties and changing the Edit Mode to Read Write.

Changing LUT Equations

The smallest logical element that can be selected is the slice. First, the block must be viewed. An individual slice can be found using the Find button on the right hand side of the window, or the array view can be navigated, and the slice selected by hand. Once the slice is selected, (shown as red in the following figure) click the Editblock button to open the Block Editor toolbar.

Figure 5-8: Viewing a Block

To prevent accidental edits, by default the internals of a slice cannot be edited. Each time a block is opened, to make it editable, select the Begin Editing button (the second button from the left in the Block Editor toolbar). This will change the window background to black.

To view the LUT equations, click on the Show/Hide Attributes button. It is the F= toolbar button. This opens a panel at the bottom of the window with the slice name, and the two equations. The valid operators are:

* Logical AND

+ Logical OR

@ Logical XOR

~ Unary NOT

The following figure shows changing the Geqn from A3*A2 to A3*~A2.?

Figure 5-9: Changing LUT Equations

Valid equations values are A1, A2, A3, and A4, representing the four address line inputs to the LUT. Parentheses can also be used to group equation sections (A4 * A1) @ ~A3). Any other names or operators will produce an error. For example:

ERROR:FPGAEDITOR:24 - "(A3*~A2 + mynet) is not a valid value for the Geqn attribute."

Once the attributes are changed, select the Saves Changes and Closes Window buttons to close the Block Editor.

Changing Block RAM Contents

The Block Editor for block RAMs (see the following figure) is very similar to the Slice Block Editor. Once in the Block Editor mode, select Show/Hide Attributes to display the contents of the RAM. The format of the data is the same as an INIT constraint in a UCF file. See the Libraries Guide for details on the INIT constraint.

Once the changes have been made, select the Saves Changes and Close Window buttons to close the window and return to the Array view.

Figure 5-10: Changing Block RAM Contents

Changing I/O Standards

To change the I/O standards, enter the Block Editor the same way as a slice or block RAM. The I/O standards are in a box in the upper-right corner of the window as shown in the next figure. To change the I/O standard, select the checkbox next to the desired I/O standard. There are also Drive Strength and Slew Rate checkboxes. Only select these when applicable. See the Libraries Guide for details on which I/O standards have selectable slew rate and drive strength.

Choose I/O standards to match the VREF voltages (or the absence of a VREF voltage) with the other I/Os in the bank or the changed I/Os will not function properly. For example, it is not possible to change an LVTTL I/O in the middle of a bank of LVTTL I/Os to the GTL standard. GTL requires VREF voltages, LVTTL does not.

Figure 5-11: Changing I/O Standards

Other Changeable Elements

A number of muxes and changeable properties in slices, IOBs, and block RAMs are eligible for an Active Partial Reconfiguration flow. Some changeable properties are: muxes that invert polarity, flip-flop initialization and reset values, pull-ups or pull-downs on external pins, or block RAM write modes. All of these properties can be modified in the actual slice, IOB, or block RAM as appropriate. It is not recommended to change any property or value that would impact routing, due to the risk of internal contention.

Making Small Design Changes Using Design Entry

Most of the changes covered in the previous section also can be made by editing the front-end of the design. Of course, making designs changes in the front-end also allows the user to edit more than just simple features such as block RAM and I/O standards with the cost of having to re-synthesize and re-implement the entire design. Once these changes have been made, the new NCD is used with the BitGen application to generate a difference-based bitstream.

Creating Difference-Based Partial Reconfiguration Bitstreams

The -g ActiveReconfig:Yes switch is required for Active Partial Reconfiguration, meaning that the device remains in full operation while the new partial bitstream is being downloaded. If the ActiveReconfig:Yes is not specified (or the -g ActiveReconfig:No is specified), then the partial bitstream contains the Shutdown and AGHIGH commands used to deassert DONE. All I/Os and internal routing should be high impedance, and writing to registers should be disabled. The changes described in this application note can be done safely with the -g ActiveReconfig option set to Yes. Additionally, the -g Persist:Yes switch is required when utilizing Partial Reconfiguration through the SelectMAP mode. This switch allows the SelectMAP pins to persist after the device is configured, which allows the SelectMAP interface to be used for reconfiguration.

A Partial Reconfiguration bitstream can be created with any other BitGen option, including the -b option (create .rbt file) or any -g options specifying configuration options except for encryption. A device that has been configured with an encrypted bitstream cannot be partially reconfigured. Similarly, a device cannot be partially reconfigured with an encrypted bitstream.

A Difference-based Partial Reconfiguration bitstream can be created with the BitGen program using the -r switch. Properly used, the -r switch produces a bitstream that contains only the differences between the input routed .ncd file and the old .bit file.

An example is:

bitgen -g ActiveReconfig:Yes -g Persist:Yes -r and_test.bit and_test2.ncd and_test2_partial.bit

This produces a configuration file (and_test2_partial.bit) that only configures the frames that are different between and_test and and_test2. When downloading this file, the and_test configuration file MUST already be programmed into the device.