Checklist for Top-Level HDL Design

The following section provides checklists for setting up design for Partial Reconfiguration.

Check that no shared signals (other than clocks) between modules.

All intermodule signals must use bus macro instantiations (4 bits each).

All I/Os in the design must be at the top-level.

Design accounts for proper handshaking to ensure no operational dependencies on the state of the reconfigurable module while it is being reconfigured.

Checklist for Module HDL Design

Check that no instantiated I/Os are inside the module.

All constants must be local to each module (not shared with other modules).

Checklist for Initial Budgeting (Floorplanned and other .ucf Constraints)

Check that areas always span full height of the device.

Areas for reconfigurable modules that communicate via bus macros must share a common boundary with no "white space" between the areas.

Boundaries fall on x=0,4,8, etc.

Minimum width is 4 slice columns.

If bus macro in leftmost position, bits 0 and 1 cannot go right-to-left.

If bus macro in rightmost position, bits 2 and 3 cannot go left-to-right.

The bus macro must be exactly centered on the module’s boundaries.

Add proper Partial Reconfiguration-specific properties to Area groups. See "Special UCF Constraints for Partial Reconfiguration".

All IOBs must be locked down.

IOBs can only be placed in sites within the columnar area for the module of which they are a member. If the area is immediately adjacent to the left or right edge of the device, all IOBs on that edge are also available for assignment to connections in that module.

All clock buffers must be locked down to specific user-defined locations.

When Floorplanning, make sure there are no pseudo-drivers or pseudo-ports. If such elements are found, correct the design HDL source to use bus macros for all intermodule communication.

Checklist for Active Module Implementation

Copy "top-level" .ucf into active module implementation directory.

Create module-specific timing constraints.

After implementation, verify signals are wholly contained within the module boundary, except those traversing boundary via the bus macro (use FPGA Editor).

Checklist for Assembled Designs

Create all possible module combinations as "assembled designs" for simulation/verification purposes.

Verify signals are wholly contained within module boundary except those traversing boundary via bus macro (use FPGA_Editor).

Checklist for Configuration

Create the full bitstream for the design.

Create the partial bitstream(s) for each module variation or the difference of two designs using BitGen.

Verify that -g ActiveReconfig and -g Persist are set to yes for the Partial Reconfiguration bitstreams.

Note: The Persist option is only needed for SelectMAP configuration.)

Verify that SelectMAP or Boundary Scan configuration modes are being used.