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BitGen Options

Following is a description of the command line options and how they affect the behavior of BitGen.

Note: For a complete description of the Xilinx Development System command line syntax, see "Command Line Syntax" in Chapter 1.

–a (Tie All Interconnect)

This options is no longer supported by BitGen for any device family.

–b (Create Rawbits File)

Create a rawbits (file_name.rbt) file. If the –g Readback option is specified in combination with the –b option, an ASCII readback command file (file_name.rba) is also generated.

The rawbits file consists of ASCII ones and zeros representing the data in the bitstream file. If you are using a microprocessor to configure a single FPGA, you can include the rawbits file in the source code as a text file to represent the configuration data. The sequence of characters in the rawbits file is the same as the sequence of bits written into the FPGA.

–bd (Update Block Rams)

–bd file_name

The –bd option updates the bitstream with the block ram content from the specified ELF or MEM file. See the "Data2MEM" chapter for more information.

–d (Do Not Run DRC)

Do not run DRC (design rule check). Without the –d option, BitGen runs a DRC and saves the DRC results in two output files: the BitGen report file (file_name.bgn) and the DRC file (file_name.drc). If you enter the –d option, no DRC information appears in the report file and no DRC file is produced.

Running DRC before a bitstream is produced detects any errors that could cause the FPGA to malfunction. If DRC does not detect any errors, BitGen produces a bitstream file (unless you use the –j option described in "–j (No BIT File)").

–f (Execute Commands File)

–f command_file

The –f option executes the command line arguments in the specified command_file. For more information on the –f option, see "–f (Execute Commands File)" in Chapter 1.

–g (Set Configuration)

The –g option specifies the startup timing and other bitstream options for Xilinx FPGAs. The debug bitstream can only be used for master and slave serial configurations. It is not valid for Boundary Scan or Slave Parallel/Select MAP. The settings for the –g option depend on the architecture of the design. These settings are described in the following section:

–g (Set Configuration—Virtex/-E/-II/-II Pro/-4 and Spartan-II/-IIE/-3/-3E)

The –g option has sub-options that represent settings you use to set the configuration for a Virtex/-E/-II/-II Pro or Spartan-II/-IIE/3 design. These options have the following syntax:

bitgen –g option:setting design.ncd design.bit design.pcf

For example, to enable Readback, use the following syntax:

bitgen –g Readback

The following sections describe the options and settings for the –g option. Each –g option is listed with supported architectures, settings, and defaults.

ActivateGCLK

Allows any partial bitstream for a reconfigurable area to have its registered elements wired to the correct clock domain. Clock domains must be minimally defined in the NCD.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

ActiveReconfig

Prevents the assertions of GHIGH and GSR during configuration. This is required for the active partial reconfiguration enhancement features

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

.

Binary

Creates a binary file with programming data only. Use this option to extract and view programming data. Any changes to the header will not affect the extraction process.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

CclkPin

Adds an internal pull-up to the Cclk pin. The Pullnone setting disables the pullup.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullnone, Pullup
Default:
Pullup

Compress

This option uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not just the .bit file. Using the Compress option does not guarantee that the size of the bitstream will shrink. Compression is enabled by setting the BitGen option –g compress; compression is disabled by not setting it.

Note that the partial bit files generated with the BitGen –r setting (detailed in Application Note XAPP290) automatically make use of the multiple frame write feature, and are compressed bitstreams.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE, Virtex-4, Spartan-3
Settings:
None
Default:
Off

ConfigRate

Virtex/-E/-II/-II Pro and Spartan-II/-IIE/-3 use an internal oscillator to generate the configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate for this clock.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan-II, Spartan-IIE, Spartan 3, Spartan-3E
Settings
4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60
Default:
4
Settings for Spartan-3/-3E
6, 3, 12, 25, 50, 100 (default is 6)
Default for Spartan-3:
6

Note: For a list of specific architecture settings, use the bitgen -h [architecture] command.The default value may vary by architecture.

CRC

The CRC option controls the generation of a Cyclic Redundancy Check value in the bitstream. When enabled, a unique CRC value is calculated based on bitstream contents. If the calculated CRC value does not match the CRC value in the bitstream, the device will fail to configure. When CRC is disabled a constant value is inserted in the bitstream in place of the CRC and the device will not calculate a CRC.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings:
Disable, Enable
Default:
Enable

DCIUpdateMode

This option controls how often the Digitally Controlled Impedance circuit attempts to update the impedance match for DCI IOSTANDARDs. This option is preferable to the FreezeDCI option because it has no effect on bitstream size and can be used with Encrypted bitstreams. The setting DCIUpdateMode:Quiet supersedes the setting FreezeDCI:Yes.

Architectures:
Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings:
As required, continuous, quiet
Default:
As required

DCMShutdown

When DCMShutdown is enabled, the digital clock manager (DCM) resets if the SHUTDOWN and AGHIGH commands are loaded into the configuration logic.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings:
Disable, Enable
Default:
Disable

DebugBitstream

If the device does not configure correctly, you can debug the bitstream using the DebugBitstream option. A debug bitstream is significantly larger than a standard bitstream. The values allowed for the DebugBitstream option are No and Yes.

Note: Use this option only if your device is configured to use slave or master serial mode

.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro,
Spartan-II, Spartan-IIE, Virtex-4, Spartan-3, Spartan-3E
Values:
No, Yes

In addition to a standard bitstream, a debug bitstream offers the following features:

  • Writes 32 0s to the LOUT register after the synchronization word
  • Loads each frame individually
  • Performs a cyclical redundancy check (CRC) after each frame
  • Writes the frame address to the LOUT register after each frame

DisableBandgap

Disables bandgap generator for DCMs to save power.

Architectures:
Virtex-II and Virtex-II Pro, Virtex-4,
Settings:
No, Yes
Default:
No

DONE_cycle

Selects the Startup phase that activates the FPGA Done signal. Done is delayed when DonePipe=Yes.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
1, 2, 3, 4, 5, 6
Default:
4

DonePin

Adds an internal pull-up to the DONE Pin pin. The Pullnone setting disables the pullup.

Use this option only if you are planning to connect an external pull-up resistor to this pin. The internal pull-up resistor is automatically connected if you do not use this option.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pullnone
Default:
Pullup

DonePipe

This option is intended for use with FPGAs being set up in a high-speed daisy chain configuration.When set to Yes, the FPGA waits on the CFG_DONE (DONE) pin to go High and then waits for the first clock edge before moving to the Done state.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

DriveDone

This option actively drives the DONE Pin high as opposed to using a pullup.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

Encrypt

Encrypts the bitstream.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4,
Settings:
No, Yes
Default:
No

Note: For more information on encryption, see the following web site: http://www.xilinx.com/products

Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3

Use these options to add delays to the global clocks. Do not use these options unless instructed to do so by Xilinx.

Architectures:
Virtex/-E/, Spartan-II/-IIE
Settings:
11111, binary string
Default:
11111

GSR_cycle

Selects the Startup phase that releases the internal set-reset to the latches, flip-flops, and BRAM output latches. The Done setting releases GSR when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes

Architectures:
Virtex/-E, Spartan-II/-IIE
Settings:
Done, 1, 2, 3, 4, 5, 6, Keep
Default:
6

.

Keep should only be used when partial reconfiguration is going to be implemented. Keep prevents the configuration state machine from asserting control signals that could cause the loss of data.

GWE_cycle

Selects the Startup phase that asserts the internal write enable to flip-flops, LUT RAMs, and shift registers. It also enables the BRAMS. Before the Startup phase both BRAM writing and reading are disabled.The Done setting asserts GWE when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes. The Keep setting is used to keep the current value of the GWE signal

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
1, 2, 3, 4, 5, 6, Done, Keep
Default:
6

.

GTS_cycle

Selects the Startup phase that releases the internal 3-state control to the I/O buffers. The Done setting releases GTS when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Done, 1, 2, 3, 4, 5, 6, Keep
Default:
5

HswapenPin

Adds a pull-up, pull-down, or neither to the HSWAP_EN pin. The Pullnone option shows there is no connection to either the pull-up or the pull-down.

Architectures:
Virtex-II, Virtex-4, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

Key0, Key1, Key2, Key3, Key4, Key5

Sets keyx for bitstream encryption. The pick option causes BitGen to select a random number for the value.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4
Settings:
Pick, hex_string
Default:
Pick

Note: For more information on encryption, see the following web site: http://www.xilinx.com/products.

KeyFile

Specifies the name of the input encryption file.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4,
Settings:
string

Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5

Sets the key sequence for keyx. The settings are equal to the following:

  • S=single
  • F=first
  • M=middle
  • L=last
    Architectures:
    Virtex-II, Virtex-II Pro, Virtex-4,
    Settings:
    S, F, M, L
    Default:
    S

LCK_cycle

Selects the Startup phase to wait until DLLs/DCMs lock. If NoWait is selected, the Startup sequence does not wait for DLLs/DCMs.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
0,1, 2, 3, 4, 5, 6, NoWait
Default:
NoWait

M0Pin

Adds an internal pull-up, pull-down or neither to the M0 pin. The following settings are available. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M0 pin.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

M1Pin

Adds an internal pull-up, pull-down or neither to the M1 pin. The following settings are available. The default is PullUp.

Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M1 pin.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

M2Pin

Adds an internal pull-up, pull-down or neither to the M2 pin. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M2 pin.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

Match_cycle

Specifies a stall in the Startup cycle until digitally controlled impedance (DCI) match signals are asserted.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings:
Auto, NoWait, 0, 1, 2, 3, 4, 5, 6
Default:
NoWait

Note: When the Auto setting is specified, BitGen searches the design for any DCI I/O standards. If DCI standards exist, BitGen will use the Match_cycle:2 setting, otherwise it will use the Match_cycle:NoWait setting.

PartialGCLK

Adds the center global clock column frames into the list of frames to write out in a partial bitstream. This option is equivalent to the PartialMask0:1 option

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Default:
<Not Specified> - no partial masks in use

.

PartialMask0, PartialMask1, PartialMask2

Generates a bitstream comprised of only the major addresses of block type <0, 1, or 2> that have enabled value in the mask. The block type is all non-block ram initialization data frames in the applicable device

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
All columns enabled, major address mask
Default:
<Not Specified> - no partial masks in use

and its derivatives. The mask is a hex value.

PartialLeft

Adds the left side frames of the device into the list of frames to write out in a partial bitstream. This includes CLB, IOB, and BRAM columns. It does not include the center global clock column.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E

PartialRight

Adds the right side frames of the device into the list of frames to write out in a partial bitstream. This includes CLB, IOB, and BRAM columns. It does not include the center global clock column.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E

Persist

This option is needed for Readback and Partial Reconfiguration using the SelectMAP configuration pins. If Persist is set to Yes, the pins used for SelectMAP mode are prohibited for use as user I/O. Refer to the datasheet for a description of SelectMAP mode and the associated pins.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

PowerdownPin

Puts the pin into “sleep” mode by specifying whether or not the internal pullup on the pin is enabled.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4,
Settings:
Pullup, Pullnone
Default:
Pullup

ProgPin

Adds an internal pull-up to the ProgPin pin. The Pullnone setting -disables the pullup. The pull-up affects the pin after configuration.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pullnone
Default:
Pullup

ReadBack

This option allows you to perform the Readback function by creating the necessary readback files.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, and Spartan-3E

When specifying the –g Readback option, the .rbb, .rbd, and .msd files are created.

If the –b option is used in conjunction with the –g Readback option, an ASCII readback command file (file_name.rba) is also generated.

Security

Selecting Level1 disables Readback. Selecting Level2 disables Readback and Partial Reconfiguration.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
None, Level1, Level2
Default:
None

SEURepair

This option supports single event upset repair by writing a debug bitstream, but with certain LOUT headers replaced with FAR headers with appropriate address adjustment.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3E
Settings:
No, Yes
Default:
No

StartCBC

Sets the starting cipher block chaining (CBC) value. The pick option causes BitGen to select a random number for the value.

Architectures:
Virtex-II, Virtex-II Pro, Virtex-4,
Settings:
Pick, hex_string
Default:
Pick

StartKey

Sets the starting key number.

Architectures:
Virtex-II, Virtex-II Pro
Settings:
0, 3
Default:
0

StartupClk

The startup sequence following the configuration of a device can be synchronized to either Cclk, a User Clock, or the JTAG Clock. The default is Cclk.

  • Cclk

    • Enter Cclk to synchronize to an internal clock provided in the FPGA device.

  • JTAG Clock

    • Enter JtagClk to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.

  • UserClk

    • Enter UserClk to synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol.

    Architectures:
    Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
    Spartan-II, Spartan-IIE, Spartan 3, and Spartan- 3E
    Settings:
    Cclk (pin—see Note), UserClk (user-supplied), JtagCLK
    Default:
    Cclk

Note: In modes where Cclk is an output, the pin is driven by an internal oscillator.

TckPin

Adds a pull-up, a pull-down or neither to the TCK pin, the JTAG test clock. Selecting one setting enables it and disables the others. The Pullnone setting shows there is no connection to either the pull-up or the pull-down.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

TdiPin

Adds a pull-up, a pull-down, or neither to the TDI pin, the serial data input to all JTAG instructions and JTAG registers. Selecting one setting enables it and disables the others. The Pullnone setting shows there is no connection to either the pull-up or the pull-down.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

TdoPin

Adds a pull-up, a pull-down, or neither to the TdoPin pin, the serial data output for all JTAG instruction and data registers. Selecting one setting enables it and disables the others. The Pullnone setting shows there is no connection to either the pull-up or the pull-down.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

TmsPin

Adds a pull-up, pull-down, or neither to the TMS pin, the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. Selecting one setting enables it and disables the others. The Pullnone setting shows there is no connection to either the pull-up or the pull-down

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pullup

UnusedPin

Adds a pull-up, a pull-down, or neither to the unused device pins and the serial data output (TDO) for all JTAG instruction and data registers. Selecting one setting enables it and disables the others. The Pullnone setting shows there is no connection to either the pull-up or the pull-down.

The following settings are available. The default is Pulldown.

Architectures:
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings:
Pullup, Pulldown, Pullnone
Default:
Pulldown

UserID

You can enter up to an 8-digit hexadecimal code in the User ID register. You can use the register to identify implementation revisions.

Architectures:
Virtex-4, Spartan-3, Spartan-3E
Settings:
0xFFFFFFFF, [hex string]
Default:
0xFFFFFFFF

–intstyle (Integration Style)

–intstyle {ise | xflow | silent}

The –intstyle option reduces screen output based on the integration style you are running. When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent. The mode sets the way information is displayed in the following ways:

–intstyle ise

This mode indicates the program is being run as part of an integrated design environment.

–intstyle xflow

This mode indicates the program is being run as part of an integrated batch flow.

–intstyle silent

This mode limits screen output to warning and error messages only.

Note: The -intstyle option is automatically invoked when running in an integrated environment, such as Project Navigator or XFLOW.

–j (No BIT File)

Do not create a bitstream file (.bit file). This option is used when you want to generate a report without producing a bitstream. For example, if you wanted to run DRC without producing a bitstream file, you would use the -j option.

Note: The .msk or .rbt files may still be created.

–l (Create a Logic Allocation File)

This option creates an ASCII logic allocation file (design.ll) for the selected design. The logic allocation file shows the bitstream position of latches, flip-flops, IOB inputs and outputs, and the bitstream position of LUT programming and Block RAMs.

In some applications, you may want to observe the contents of the FPGA internal registers at different times. The file created by the –l option helps you identify which bits in the current bitstream represent outputs of flip-flops and latches. Bits are referenced by frame and bit number within the frame.

The iMPACT tool uses the design.ll file to locate signal values inside a readback bitstream.

–m (Generate a Mask File)

Creates a mask file. This file determines which bits in the bitstream should be compared to readback data for verification purposes.

–n (Save a Tied Design)

This option is no longer supported by BitGen for any device family.

–r (Create a Partial Bit File)

–r bit_file

The –r option is used to create a partial bit file. It takes that bit file and compares it to the .ncd file given to bitgen. Instead of writing out a full bit file, it only writes out the part of the bit file that is different from the original bit file given.

–t (Tie Unused Interconnect)

This option is no longer supported by BitGen for any device family.

–u (Use Critical Nets)

This option is no longer supported by BitGen for any device family.

–w (Overwrite Existing Output File)

Enables you to overwrite an existing BitGen output file. See "BitGen Output Files" for additional information.

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