SRL16_1

16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock

Architectures Supported
SRL16_1
Spartan-II, Spartan-IIE	Primitive
Spartan-3	Primitive
Virtex, Virtex-E	Primitive
Virtex-II, Virtex-II Pro, Virtex-II Pro X	Primitive
XC9500, XC9500XV, XC9500XL	No
CoolRunner XPLA3	No
CoolRunner-II	No

SRL16_1 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted. See “Static Length Mode” and “Dynamic Length Mode” in “SRL16”.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. During subsequent High-to-Low clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.


Inputs			Output
Am	CLK	D	Q
Am	X	X	Q(Am)
Am		D	Q(Am-1)
m= 0, 1, 2, 3

Usage

For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template


-- SRL16_1: 16-bit shift register LUT operating on negedge of clock
   --          All FPGAs
   -- Xilinx  HDL Language Template version 6.1i
   
   SRL16_1_inst : SRL16_1
   -- The following generic declaration is only necessary if 
-- you wish to change the initial.
   -- contents of the SRL to anything other than all zero's.
   generic map (
      INIT => X"0000")
   port map (
Q => Q,       -- SRL data output
      A0 => A0,     -- Select[0] input
      A1 => A1,     -- Select[1] input
      A2 => A2,     -- Select[2] input
      A3 => A3,     -- Select[3] input
      CLK => CLK,   -- Clock input
      D => D        -- SRL data input
   );


   -- End of SRL16_1_inst instantiation

Verilog Instantiation Template


   SRL16_1 SRL16_1_inst (
      .Q(Q),       // SRL data output
      .A0(A0),     // Select[0] input
      .A1(A1),     // Select[1] input
      .A2(A2),     // Select[2] input
      .A3(A3),     // Select[3] input
      .CLK(CLK),   // Clock input
      .D(D)        // SRL data input
   );

// The following defparam declaration is only necessary if you wish to
// change the initial contents of the SRL to anything other than all
// zero's.  If the instance name to the SRL is changed, that change
// needs to be reflected in the defparam statements.

   defparam SRL16_1_inst.INIT = 16'h0000;


// End of SRL16_1_inst instantiation

Commonly Used Constraints

BEL, U_SET, INIT