VHDL/Verilog Libraries and Models

The five simulation points listed previously require the UNISIM, CORE Generator™ (Xilinx®CoreLib), SmartModel and SIMPRIM libraries.

The first point, RTL simulation, is a behavioral description of your design at the register transfer level. RTL simulation is not architecture-specific unless your design contains instantiated UNISIM, or CORE Generator™ components. To support these instantiations, Xilinx® provides a functional UNISIM library, a CORE Generator™ Behavioral Xilinx®CoreLib library and a SmartModelLibrary™. You can also instantiate CORE Generator™ components if you do not want to rely on the module generation capabilities of your synthesis tool, or if your design requires larger memory structures.

The second simulation point is post-synthesis (pre-NGDBuild) gate-level simulation. If the UNISIM library and CORE Generator™ components are used, then the UNISIM, the Xilinx®CoreLib and SmartModel Libraries must all be used. The synthesis tool must write out the HDL netlist using UNISIM primitives. Otherwise, the synthesis vendor provides its own post-synthesis simulation library, which is not supported by Xilinx.

The third, fourth, and fifth points (post-NGDBuild, post-map, and post-route) use the SIMPRIM and/or the SmartModel Libraries. The following table indicates what library is required for each of the five simulation points.

Locating Library Source Files

The following table provides information on the location of the simulation library source files, as well as the order for a typical compilation.

Table 6-3: Simulation Phase Library Information
Simulation Point	Compilation Order of Library Required
RTL	UNISIM XilinxCoreLib SmartModel
Post-Synthesis	UNISIM XilinxCoreLib SmartModel
Post-NGDBuild	SIMPRIM SmartModel
Post-Map	SIMPRIM SmartModel
Post-Route	SIMPRIM SmartModel

Table 6-4: Simulation Library Source Files
Library	Location of Source Files		Compile Order
Library	Verilog	VITAL VHDL	Verilog	VITAL VHDL
UNISIM Spartan-II™, Spartan-IIE™, Spartan-3™, Virtex™, Virtex™-E, Virtex-II™, Virtex-II Pro™, Virtex-II Pro™X, Virtex-4™, Xilinx IBM FPGA Core	$XILINX/verilog/src/unisims - Unix/Linux %XILINX%\verilog \src\unisims - Windows	$XILINX/vhdl/ src/unisims - Unix/Linux %XILINX%\vhdl\ src\unisims - Windows	No special compilation order required for Verilog libraries	Required; typical compilation order: unisim_VCOMP.vhd unisim_VPKG.vhd unisim_VITAL.vhd
UNISIM 9500™, CoolRunner™, CoolRunner-II™	$XILINX/verilog/src/uni9000-Unix/Linux %XILINX%\verilog\src\uni9000-Windows	$XILINX/vhdl/ src/unisims	No special compilation order required for Verilog libraries	Required; typical compilation order: unisim_VCOMP.vhd unisim_VPKG.vhd unisim_VITAL.vhd
XilinxCoreLib FPGA Families only	$XILINX/verilog/src/XilinxCore-Lib-Unix/Linux %XILINX%\verilog\src\XilinxCoreLib-Windows	$XILINX/vhdl/ src/XilinxCore-Lib-Unix/Linux %XILINX%\vhdl\ src\XilinxCoreLib-Windows	No special compilation order required for Verilog libraries	Compilation order required; See the vhdl_analyze_order file located in $XILINX/vhdl/src/ XilinxCoreLib/ -Unix/Linux $XILINX/vhdl/src/ XilinxCoreLib/-Windows for the required compile order
SmartModel Virtex-II Pro™ Virtex-II Pro X™ Virtex-4™	$XILINX/ smartmodel/ <platform>/ wrappers/ <simulator>-Unix/Linux %XILINX%\ smartmodel\ <platform>\ wrappers\ <simulator>-Unix/Linux	$XILINX/ smartmodel/ <platform>/ wrappers/ <simulator>-Unix/Linux$XILINX/ smartmodel/ platform/ wrappers/ simulator %XILINX%\ smartmodel\ <platform>\ wrappers\ <simulator>-Unix/Linux	No special compilation order required for Verilog libraries	Required. Typical compilation order for Functional Simulation: unisim_VCOMP.vhd smartmodel_wrappers.vhd unisim_SMODEL.vhd Typical compilation order for Timing Simulation: simprim_Vcomponents.vhd (Simprim_Vcomponents_mti.vhd) - for MTI only smartmodel_wrappers.vhd simprim_SMODEL.vhd (simprim_SMODEL_mti.vhd) - for MTI only
SIMPRIM (All Xilinx® Technologies)	$XILINX/verilog/src/simprims-Unix/Linux %XILINX%\verilog\src\simprims-Windows	$XILINX/vhdl/ src/simprims-Unix/Linux %XILINX%\vhdl\ src\simprims-Windows	No special compilation order required for Verilog libraries	Required; typical compilation order: simprim_Vcomponents.vhd (simprim_Vcomponents_mti.vhd) - for MTI only (simprim_Vpackage_mti.vhd) - for MTI only simprim_Vpackage.vhd simprim_VITAL.vhd (simprim_VITAL_mti.vhd) - for MTI only

Using the UNISIM Library

The UNISIM Library is used for functional simulation only. This library includes all of the Xilinx® Unified Library primitives that are inferred by most synthesis tools. In addition, the UNISIM Library includes primitives that are commonly instantiated, such as DCMs, BUFGs and GTs. You should generally infer most design functionality using behavioral RTL code unless the desired component is not inferrable by your synthesis tool, or you want to take manual control of mapping and/or placement of a function.

UNISIM Library Structure

The UNISIM library structure is different for VHDL and Verilog. The VHDL UNISIM library is split into four files containing the component declarations (unisim_VCOMP.vhd), package files (unisim_VPKG.vhd), entity and architecture declarations (unisim_VITAL.vhd), and SmartModel declarations (unisim_SMODEL.vhd). All primitives for all Xilinx® device families are specified in these files. The VHDL UNISIM Library source files are located at $XILINX/vhdl/src/unisims - Unix/Linux

For Verilog, each library component is specified in a separate file. The reason for this is to allow automatic library expansion using the `uselib compiler directive or the –y library specification switch. All Verilog module names and file names are all upper case (i.e. module BUFG would be BUFG.v, module IBUF would be IBUF.v). Since Verilog is a case-sensitive language, ensure that all UNISIM primitive instantiations adhere to this upper-case naming convention.

The library sources are split into two directories in which the FPGA device families (Spartan-II™, Spartan-IIE™, Spartan-3™, Virtex™, Virtex™- E, Virtex-II™, Virtex-II Pro™, Virtex-II Pro X™, Virtex-4™ and Xilinx® IBM FPGA Core™) are located at $XILINX/verilog/src/unisims, and the CPLD device families (XC9500XL™, XC9500XV™, CoolRunner-XPLA3™, CoolRunner-II™) are located at

Using the CORE Generator™ Xilinx®CoreLib Library

The Xilinx® CORE Generator™ is a graphical intellectual property design tool for creating high-level modules like FIR Filters, FIFOs and CAMs, as well as other advanced IP. You can customize and pre-optimize modules to take advantage of the inherent architectural features of Xilinx® FPGA devices, such as block multipliers, SRLs, fast carry logic, and on-chip, single-port or dual-port RAM. You can also select the appropriate HDL model type as output to integrate into your HDL design.

The CORE Generator™ HDL library models are used for RTL simulation. The models do not use library components for global signals.

CORE Generator™ Library Structure

Using the SIMPRIM Library

The SIMPRIM library is used for post Ngdbuild (gate level functional), post-Map (partial timing), and post-place-and-route (full timing) simulations. This library is architecture independent.

SIMPRIM Library Structure

The SmartModel Libraries™ are used to model very complex functions of modern FPGA devices such as the PowerPC® (PPC) and the RocketIO™. SmartModels are encrypted source files that communicate with simulators via the SWIFT interface. The SmartModel Libraries™ are located at $XILINX/smartmodel or %XILINX%\smartmodel, and require additional installation steps to properly install on your system. Additional setup within the simulator may also be required. See "Using SmartModels" chapter for more information on proper installation and setup of the SmartModel Libraries™.