Running NetGen

Xilinx® provides a program that can create a verification netlist file from your design files. You can run the netlist writer from Project Navigator, XFLOW, or the command line. Each method is described in the following sections.

Creating a Simulation Netlist

You can create a timing simulation netlist from Project Navigator, XFLOW, or from the command line, as described in this section.

From Project Navigator

Highlight the top level design in the Sources in Project window.

In the Processes for Source window, click on the “+” sign next to the Implement Design process, and then click on the “+” sign next to the Place & Route process.

If any default options need to be changed, right-click on the Generate Post Place & Route Simulation Model process and select Properties. Choose the options from the window that opens.

Note: Project Navigator shows only the options that apply to your specific design flow. For example, if you have created a Verilog project, Project Navigator shows you only the options for creating a Verilog netlist.

Simulation Model Target

The Simulation Model Target property allows you to select the target simulator for the simulation netlist. All supported simulators are listed as well as a "generic" VHDL or Verilog netlist for other simulators.

Post Place & Route Simulation Model Name

The Post Place & Route Simulation Model Name property allows you to designate a name for the generated simulation netlist. This only affects the file name for the written netlist and does not affect the entity or module name.

By default, this field is left blank, and the simulation netlist name is top_level_name_timesim.

Generate Multiple Hierarchical Netlist Files

The Generate Multiple Hierarchical Netlist Files property allows the netlister to generate separate gate-level netlists and SDF files (if applicable) for each hierarchy level in the design that is designated with a KEEP_HIERARCHY attribute. This allows for piece-wise verification of a design. See the "Design Hierarchy and Simulation" section for more details on this option.

The default for this option is Off (checkbox is unchecked). This option must be used with Correlate Simulation Data to Input Design enabled.

Use Automatic DO File for ModelSim™ Simulation

This option enables Project Navigator to create and use a batch script file for compiling and simulating your test bench and design files when the ModelSim™ simulator is invoked.

The default for this option is On (checkbox is checked). This option is only relevant if you invoke the ModelSim™ simulator from Project Navigator.

The following options appear if the Advanced Process Settings are enabled in Project Navigator.

Bring Out Global Tristate Net as a Port

The Bring Out Global Tristate Net as a Port option causes NetGen to bring out the global tristate signal (which forces all FPGA outputs to the high-impedance state) as a port on the top-level design module in the output netlist. Specifying the port name allows you to match the port name you used in the front end if being driven by a TOCBUF. This option should only be used if the global tristate net is not driven by a STARTUP/STARTBUF block. For more information on this option, see the "Understanding the Global Reset and Tristate for Simulation" section.

Global Tristate Port Name

The Global Tristate Port Name property allows you to specify a port name to match the port name you used in the front end if a TOCBUF component was used.

Bring Out Global Set/Reset Net as a Port

The Bring Out Global Set/Reset Net as a Port property causes NetGen to bring out the Global Set/Reset signal (which is connected to all flip-flops and latches in the physical design) as a port on the top-level design module in the output netlist. Specifying the port name allows you to match the port name you used in the front end if a ROCBUF component was used. This option should only be used if the global set/reset net is not driven by a STARTUP/STARTBUF block. For more information on this option, see the "Understanding the Global Reset and Tristate for Simulation" section.

Global Set/Reset Port Name

The Global Set/Reset Port Name property allows you to specify a port name to match the port name you used in the front end if a ROCBUF component was used.

Generate Testbench File (VHDL Only)

The Generate Testbench Template File property creates a test bench file. The file has a .tvhd extension and displays in the "Sources in Project" window.

Generate Testfixture File (Verilog Only)

The Generate Testfixture Template File property generates a test fixture file. The file has a .tv extension, and it is a ready-to-use template test fixture that the Verilog file bases on the input design file.

Rename Top Level Entity To (VHDL Only)

This option allows you to change the name of the top-level entity in the structural VHDL file. By default, the output files inherit the top entity name from the input design file.

Rename Top Level Module to (Verilog only)

This option allows you to change the name of the top-level module in the structural Verilog file. By default, the output files inherit the top module name from the input design file.

Rename Top Level Architecture To (VHDL Only)

This option allows you to rename the architecture name generated by NetGen VHDL. The default architecture name for each entity in the netlist is STRUCTURE.

Device Speed Grade/Selecty ABS Minimum

This option allows you to change the targeted speed grade for the output simulation netlist without re-running place and route. This option also allows you to create a simulation netlist with absolute minimum timing numbers if they are available for the target device.

Retain Hierarchy

This option, when enabled, allows the netlister to write a verification netlist in which the netlist will retain each level of design hierarchy that was specified on the KEEP_HIERARCHY attribute. When disabled, it removes all hierarchy from the output simulation netlist, and writes out a flat design.

The default for this option is ON.

Tristate on Configuration Pulse Width (VHDL Only)

This option specifies the pulse width, in nanoseconds, for the TOC component. You must specify a positive integer to stimulate the component properly. This option is disabled if you are controlling the global tristate via a port (using the "Bring Out Global Tristate Net as a Port" option). For more information on this option, see the "Understanding the Global Reset and Tristate for Simulation" section. By default, the TOC pulse width is set to 0 ns.

Reset On Configuration Pulse Width (VHDL Only)

This option specifies the pulse width, in nanoseconds, for the ROC component in the simulation netlist. You must specify a positive integer to stimulate the component properly. This option is disabled if you are controlling the global reset via a port (using the "Bring Out Global Set/Reset Net as a Port" option). For more information on this option, see the "Understanding the Global Reset and Tristate for Simulation" section. By default, the ROC pulse width is set to 100 ns.

Rename Design Instance in Testbench File To

This option specifies the name of the top-level design instance name appearing within the output test bench template file if the "Generate Testbench/Testfixture File" option is selected. The option allows you to match the top-level instance name to the name specified in your RTL test bench file. The default name for the test bench instance is UUT.

Include 'uselib Directive in Verilog File (Verilog Only)

The Include 'uselib Directive in Verilog File property causes ISE to write a library path pointing to the SIMPRIM library into the output Verilog (.v) file. In general, Xilinx® only suggests that you use this option with the Verilog-XL simulator when simulations are performed on the same network as where the ISE software exists. By default, this field is set to Off (checkbox is blank).

Include $sdf_annotate Function in Verilog File

Path used in $sdf_annotate (Verilog Only)

This option allows you to specify a path to the SDF file that you want written to the $sdf_annotate function in the Verilog netlist file. If a full path is not specified, it writes the full path of the current work directory and the SDF file name to the $sdf_annotate file.

The default path for the SDF file is in the same directory in which the Verilog simulation netlist resides.

Include SIMPRIM Models in Verilog File

Do Not Escape Signal and Instance Names in Netlist (Verilog only)

Specifies whether to use the Verilog escape naming method for signal names with invalid characters or to replace the invalid characters with underscores in order to create a valid netlist. When this property is set to True (checkbox is checked), name escaping does not occur, and, for example, the net name "\p140/empty" becomes "p140_empty" because the forward slash in an invalid character. Most simulators can use the Verilog escape names; however, this property allows for netlist compatibility for those that do not.

Global Disable of X-generation for Simulation (VHDL Only)

This option is used to disable X-generation by all registers in the design when a timing violation occurs. If this option is set, all registers in the design retain their last value when a timing violation occurs. For more information on this option, see "Disabling ‘X’ Propagation" in this manual. The default value for this option is OFF.

Note: This option should be used sparingly. The preferred method is to set ASYN_REG constraint rather than to use this option. Details on ASYNC_REG is provided in the "Disabling 'X' Propagation" in this manual.

Generate Architecture Only (No Entry Declaration)

Specifies whether to create an entity for each level of hierarchy in the design, or whether to generate the architecture portion only. This option is useful when generics are declared in the top-level entity declaration in the original RTL design as it allows the re-use of the original entity declaration for proper linking of the structural design to the test bench file. By default, this property is set to False (checkbox is unchecked), and both entity and architectures are created in the resulting netlist.

Other NetGen Command Line Options

This allows the user to specify options for NetGen that are not available from the above options.

Double-click Generate Post Place & Route Simulation Model. Project Navigator now runs through the steps required to produce the back-annotated simulation netlist.

From XFLOW

To display the available options for XFLOW, and for a complete list of the XFLOW option files, type "xflow" at the prompt without any arguments. For complete descriptions of the options and the option files, see the Development System Reference Guide.

Open a command terminal and change directory to the project directory.

Type the following at the command prompt:

To create a functional simulation (Post NGD) netlist from an input design EDIF file:

> xflow -fsim option_file.opt design_name.edif

To create a timing simulation (post PAR) netlist from an input EDIF design file:

> xflow -implement option_file -tsim option_file design_name.edf

To create a timing simulation (Post PAR) netlist from an NCD file:

> xflow -tsim option_file.opt design_name.ncd

XFLOW runs the appropriate programs with the options specified in the option file. To change the options, run xflow first with the –norun switch to have XFLOW copy the option file(s) to the project directory. Then edit the appropriate option file to modify the run parameters for the flow. For more information on running XFLOW, see the Development System Reference Guide.

Running NetGen

Creating a Simulation Netlist

From Project Navigator

From XFLOW

From Command Line or Script File