XFLOW Flow Types

A “flow” is a sequence of programs invoked to synthesize, implement, simulate, and configure a design. For example, to implement an FPGA design the design is run through the NGDBuild, MAP, and PAR programs.

“Flow types” instruct XFLOW to execute a particular flow as specified in the relative flow file. (For more information on flow files, see, "Flow Files".) You can enter multiple flow types on the command line to achieve a desired flow. This section describes the flow types you can use.

Note: All flow types require that an option file be specified. If you do not specify an option file, XFLOW issues an error.

–assemble (Module Assembly)

–assemble option_file –pd pim_directory_path

Note: This flow type supports FPGA device families only.

This flow type runs the final phase of the Modular Design flow. In this “Final Assembly” phase, the team leader assembles the top-level design and modules into one NGD file and then implements the file.

Note: Use of this option assumes that you have completed the Initial Budgeting and Active Implementation phases of Modular Design. See "–implement (Implement an FPGA)" and "–initial (Initial Budgeting of Modular Design)" for details.

This flow type invokes the fpga.flw flow file and runs NGDBuild to create the NGD file that contains logic from the top-level design and each of the Physically Implemented Modules (PIMs). XFLOW then implements the NGD file by running MAP and PAR to create a fully expanded NCD file.

The working directory for this flow type should be the top-level design directory. You can either run the –assemble flow type from the top-level directory or use the –wd option to specify this directory. Specify the path to the PIMs directory after the –pd option. If you do not use the –pd option, XFLOW searches the working directory for the PIM files.The input design file should be the NGO file for the top-level design. See "Modular Design" chapter for more information.

Xilinx provides the following option files for use with this flow type. These files allow you to optimize your design based on different parameters.

Table 25-4: Option Files for –assemble Flow Type

Option Files	Description
fast_runtime.opt	Optimized for fastest runtimes at the expense of design performance Recommended for medium to slow speed designs
balanced.opt	Optimized for a balance between speed and high effort
high_effort.opt	Optimized for high effort at the expense of longer runtimes Recommended for creating designs that operate at high speeds

The following example shows how to assemble a Modular Design with a top-level design named “top”:

xflow –p xc2v250fg256-5 –assemble balanced.opt –pd ../pims top.ngo

–config (Create a BIT File for FPGAs)

–config option_file

This flow type creates a bitstream for FPGA device configuration using a routed design. It invokes the fpga.flw flow file and runs the BitGen program.

Xilinx provides the bitgen.opt option file for use with this flow type.

To use a netlist file as input, you must use the –implement flow type with the –config flow type. The following example shows how to use multiple flow types to implement and configure an FPGA:

xflow –p xc2v250fg256-5 –implement balanced.opt –config bitgen.opt testclk.edf

To use this flow type without the –implement flow type, you must use a placed and routed NCD file as input.

–ecn (Create a File for Equivalence Checking)

–ecn option_file

This flow type generates a file that can be used for formal verification of an FPGA design. It invokes the fpga.flw flow file and runs NGDBuild and NetGen to create a netgen.ecn file. This file contains a Verilog netlist description of your design for equivalence checking.

Xilinx provides the following option files for use with this flow type.

Table 25-5: Option Files for –ecn Flow Type

Option Files	Description
conformal_verilog.opt	Option file for equivalence checking for conformal
formality_verilog.opt	Option file for equivalence checking for formality

–fit (Fit a CPLD)

–fit option_file

This flow type incorporates logic from your design into physical macrocell locations in a CPLD. It invokes the cpld.flw flow file and runs NGDBuild and CPLDfit to create a JED file.

Xilinx provides the following option files for use with this flow type. These files allow you to optimize your design based on different parameters.

Table 25-6: Option Files for –fit Flow Type

Option Files	Description
balanced.opt	Optimized for a balance between speed and density
speed.opt	Optimized for speed
density.opt	Optimized for density

The following example shows how to use a combination of flow types to fit a design and generate a VHDL timing simulation netlist for a CPLD.

xflow -p xc2c64-4-cp56 -fit balanced.opt -tsim generic_vhdl.opt main_pcb.edn

–fsim (Create a File for Functional Simulation)

–fsim option_file

Note: The –fsim flow type can be used alone or with the –synth flow type. It cannot be combined with the –implement, –tsim, –fit, or –config flow types.

This flow type generates a file that can be used for functional simulation of an FPGA or CPLD design. It invokes the fsim.flw flow file and runs NGDBuild and NetGen to create a func_sim.edn, func_sim.v, or func_sim.vhdl file. This file contains a netlist description of your design in terms of Xilinx simulation primitives. You can use the functional simulation file to perform a back-end simulation with a simulator.

Xilinx provides the following option files, which are targeted to specific vendors, for use with this flow type.

Table 25-7: Option Files for –fsim Flow Type

Option File	Description
generic_vhdl.opt	Generic VHDL
modelsim_vhdl.opt	Modelsim VHDL
generic_verilog.opt	Generic Verilog
modelsim_verilog.opt	Modelsim Verilog
nc_verilog.opt	NC Verilog
verilog_xl.opt	Verilog-XL
vcs_verilog.opt	VCS Verilog
nc_vhdl.opt	NC VHDL
scirocco_vhdl.opt	Scirocco VHDL

The following example shows how to generate a Verilog functional simulation netlist for an FPGA design.

xflow -p xc2v250fg256-5 -fsim generic_verilog.opt testclk.v

–implement (Implement an FPGA)

–implement option_file

This flow type implements your design. It invokes the fpga.flw flow file and runs NGDBuild, MAP, PAR, and then TRACE. It outputs a placed and routed NCD file.

Xilinx provides the following option files for use with this flow type. These files allow you to optimize your design based on different parameters.

Table 25-8: Option Files for –implement Flow Type

Option Files	Description
fast_runtime.opt	Optimized for fastest runtimes at the expense of design performance Recommended for medium to slow speed designs
balanced.opt	Optimized for a balance between speed and high effort
high_effort.opt	Optimized for high effort at the expense of longer runtimes Recommended for creating designs that operate at high speeds
overnight.opt	Multi-pass place and route (MPPR) overnight mode
weekend.opt	Multi-pass place and route (MPPR) weekend mode
exhaustive.opt	Multi-pass place and route (MPPR) exhaustive mode

The following example shows how to use the –implement flow type:

xflow -p xc2v250fg256-5 -implement balanced.opt testclk.edf

–initial (Initial Budgeting of Modular Design)

–initial budget.opt

Note: This flow type supports FPGA device families only.

This flow type runs the first phase of the Modular Design flow. In this “Initial Budgeting” phase, the team leader generates an NGO and NGD file for the top-level design. The team leader then sets up initial budgeting for the design. This includes assigning top-level timing constraints as well as location constraints for various resources, including each module.

This flow type invokes the fpga.flw flow file and runs NGDBuild to create an NGO and NGD file for the top-level design with all of the instantiated modules represented as unexpanded blocks. After running this flow type, assign constraints for your design using the Floorplanner and Constraints Editor tools.

Note: You cannot use the NGD file produced by this flow for mapping.

The working directory for this flow type should be the top-level design directory. You can either run the –initial flow type from the top-level design directory or use the –wd option to specify this directory. The input design file should be an EDIF netlist or an NGC netlist from XST. If you use an NGC file as your top-level design, be sure to specify the .ngc extension as part of your design name. See "Modular Design" chapter for more information.

Xilinx provides the budget.opt option file for use with this flow type.

The following example shows how to run initial budgeting for a modular design with a top-level design named “top”:

xflow –p xc2v250fg256-5 –initial budget.opt top.edf

–module (Active Module Implementation)

–module option_file –active module_name

Note: This flow type supports FPGA device families only. You cannot use NCD files from previous software releases with Modular Design in the current release. You must generate new NCD files with the current release of the software.

This flow type runs the second phase of the Modular Design flow. In this “Active Module Implementation” phase, each team member creates an NGD file for his or her module, implements the NGD file to create a Physically Implemented Module (PIM), and publishes the PIM using the PIMCreate command line tool.

This flow type invokes the fpga.flw flow file and runs NGDBuild to create an NGD file with just the specified “active” module expanded. This output NGD file is named after the top-level design. XFLOW then runs MAP and PAR to create a PIM.

Then, you must run PIMCreate to publish the PIM to the PIMs directory. PIMCreate copies the local, implemented module file, including the NGO, NGM and NCD files, to the appropriate module directory inside the PIMs directory and renames the files to module_name.extension. To run PIMCreate, type the following on the command line or add it to your flow file:

pimcreate pim_directory -ncd design_name_routed.ncd

The working directory for this flow type should be the active module directory. You can either run the –module flow type from the active module directory or use the –wd option to specify this directory. This directory should include the active module netlist file and the top-level UCF file generated during the Initial Budgeting phase. You must specify the name of the active module after the –active option, and use the top-level NGO file as the input design file. See "Modular Design" chapter for more information.

Xilinx provides the following option files for use with this flow type. These files allow you to optimize your design based on different parameters.

Table 25-9: Option Files for –module Flow Type

Option Files	Description
fast_runtime.opt	Optimized for fastest runtimes at the expense of design performance Recommended for medium to slow speed designs
balanced.opt	Optimized for a balance between speed and high effort
high_effort.opt	Optimized for high effort at the expense of longer runtimes Recommended for designs that operate at high speeds

The following example shows how to implement a module.

xflow –p xc2v250fg256-5 –module balanced.opt –active controller ~teamleader/mod_des/implemented/top/top.ngo

–mppr (Multi-Pass Place and Route for FPGAs)

–mppr option_file

This flow type runs multiple place and route passes on your FPGA design. It invokes the fpga.flw flow file and runs NGDBuild, MAP, multiple PAR passes, and TRACE. After running the multiple PAR passes, XFLOW saves the “best” NCD file in the subdirectory called mppr.dir. (Do not change the name of this default directory.) This NCD file uses the naming convention placer_level_router_level_cost_table.ncd.

XFLOW then copies this “best” result to the working directory and renames it design_name.ncd. It also copies the relevant DLY, PAD, PAR, and XPI files to the working directory.

Note: By default, XFLOW does not support the multiple-node feature of the PAR Turns Engine. If you want to take advantage of this UNIX-specific feature, you can modify the appropriate option file to include the PAR –m option. See "–m (Multi-Tasking Mode)" in Chapter 11 for more information.

Xilinx provides the following option files for use with this flow type. These files allow you to set how exhaustively PAR attempts to place and route your design.

Note: Each place and route iteration uses a different “cost table” to create a different NCD file. There are 100 cost tables numbered 1 through 100. Each cost table assigns weighted values to relevant factors such as constraints, length of connection, and available routing resources.

Table 25-10: Option Files for –mppr Flow Type

Option Files	Description
overnight.opt	Runs 10 place and route iterations
weekend.opt	Runs place and route iterations until the design is fully routed or until 100 iterations are complete
exhaustive.opt	Runs 100 place and route iterations

The following example shows how to use the -mppr flow type:

xflow –p xc2v250fg256-5 –mppr overnight.opt testclk.edf

–sta (Create a File for Static Timing Analysis)

–sta option_file

This flow type generates a file that can be used to perform static timing analysis of an FPGA design. It invokes the fpga.flw flow file and runs NGDBuild and NetGen to generate a Verilog netlist compatible with supported static timing analysis tools.

Xilinx provides the following option file for use with this flow type.

Table 25-11: Option Files for –sta Flow Type

Option File	Description
primetime_verilog.opt	Option file for static timing analysis of Primetime.

–synth

–synth option_file

Note: When using the –synth flow type, you must specify the –p option.

This flow type allows you to synthesize your design for implementation in an FPGA, for fitting in a CPLD, or for compiling for functional simulation. The input design file can be a Verilog or VHDL file.

You can use the -synth flow type alone or combine it with the -implement, -fit, or -fsim flow type. If you use the -synth flow type alone, XFLOW invokes either the fpga.flw or cpld.flw file and runs XST to synthesize your design. If you combine the -synth flow type with the -implement, -fit, or -fsim flow type, XFLOW invokes the appropriate flow file, runs XST to synthesize your design, and processes your design as described in one of the following sections:

"–implement (Implement an FPGA)"
"–fit (Fit a CPLD)"
"–fsim (Create a File for Functional Simulation)"

Synthesis Types

There are three different synthesis types that are described in the following sections.

XST

Use the following example to enter the XST command:

xflow -p xc2v250fg256-5 -synth xst_vhdl.opt design_name.vhd

If you have multiple VHDL or Verilog files, you can use a PRJ file that references these files as input. Use the following example to enter the PRJ file:

xflow -p xc2v250fg256-5 -synth xst_vhdl.opt design_name.prj

Leonardo Spectrum

Use the following example to enter the Leonardo Spectrum command:

xflow -p xc2v250fg256-5 -synth leonardospectrum_vhdl.opt design_name.vhd

If you have multiple VHDL files, you must list all of the source files in a text file, one per line and pass that information to XFLOW using the –g (Specify a Global Variable) option. Assume that the file that lists all source files is filelist.txt and design_name.vhd is the top level design. Use the following example:

xflow -p xc2v250fg256-5 -g srclist:filelist.txt -synth leonardospectrum_vhdl.opt design_name.vhd

The same rule applies for Verilog too.

Synplicity

Use the following example to enter the Synplicity command:

xflow -p xc2v250fg256-5 -synth synplicity_vhdl.opt design_name.vhd

If you have multiple VHDL files, you must list all the source files in a text file, one per line and pass that information to XFLOW using the –g (Specify a Global Variable) option. Assume that the file that lists all source files is filelist.txt and design_name.vhd is the top level design. Use the following example:

xflow -p xc2v250fg256-5 -g srclist:filelist.txt -synth synplicity_vhdl.opt design_name.vhd

The same rule applies for Verilog too.

The following example shows how to use a combination of flow types to synthesize and implement a design:

xflow -p xc2v250fg256-5 -synth xst_vhdl.opt -implement balanced.opt testclk.prj

Option Files for -synth Flow Types

Xilinx provides the following option files for use with the –synth flow type. These files allow you to optimize your design based on different parameters.

Table 25-12: Option Files for –synth Flow Type

Option File	Description
xst_vhdl.opt leonardospectrum_vhdl.opt synplicity_vhdl.opt	Optimizes a VHDL source file for speed, which reduces the number of logic levels and increases the speed of the design
xst_verilog.opt leonardospectrum_verilog.opt synplicity_verilog.opt	Optimizes a Verilog source file for speed, which reduces the number of logic levels and increases the speed of the design
xst_mixed.opt	Optimizes a mixed level VHDL and Verilog source file for speed, which reduces the number of logic levels and increases the speed of the design.

The following example shows how to use a combination of flow types to synthesize and implement a design:

xflow –p xc2v250fg256-5 –synth xst_vhdl.opt -implement balanced.opt testclk.prj

–tsim (Create a File for Timing Simulation)

–tsim option_file

This flow type generates a file that can be used for timing simulation of an FPGA or CPLD design. It invokes the fpga.flw or cpld.flw flow file, depending on your target device. For FPGAs, it runs NetGen. For CPLDs, it runs TSim and NetGen. This creates a time_sim.v or time_sim.vhdl file that contains a netlist description of your design in terms of Xilinx simulation primitives. You can use the output timing simulation file to perform a back-end simulation with a simulator.

Xilinx provides the following option files, which are targeted to specific vendors, for use with this flow type.

Table 25-13: Option Files for –tsim Flow Type

Option File	Description
generic_vhdl.opt	Generic VHDL
modelsim_vhdl.opt	Modelsim VHDL
generic_verilog.opt	Generic Verilog
modelsim_verilog.opt	Modelsim Verilog
scirocco_vhdl.opt	Scirocco VHDL
nc_verilog.opt	NC Verilog
verilog_xl.opt	Verilog-XL
vcs_verilog.opt	VCS Verilog
nc_vhdl.opt	NC VHDL

The following example shows how to use a combination of flow types to fit and perform a VHDL timing simulation on a CPLD:

xflow -p xc2c64-4-cp56 -fit balanced.opt -tsim generic_vhdl.opt main_pcb.vhd

Flow Files

When you specify a flow type on the command line, XFLOW invokes the appropriate flow file and executes some or all of the programs listed in the flow file. These files have a .flw extension. Programs are run in the order specified in the flow file.

Xilinx provides three flow files. You can edit these flow files, to add a new program, modify the default settings, and add your own commands between Xilinx programs. However, you cannot create new flow files of your own.

The following table lists the flow files invoked for each flow type.

Table 25-14: Xilinx Flow Files

Flow Type	Flow File	Devices	Flow Phase	Programs Run
–synth	fpga.flw	FPGA	Synthesis	XST, Synplicity, Leonardo Spectrum
–initial			Modular Design Initial Budgeting Phase	NGDBuild
–module			Modular Design Active Module Implementation Phase	NGDBuild, MAP, PAR
–assemble			Modular Design Final Assembly Phase	NGDBuild, MAP, PAR
–implement			Implementation	NGDBuild, MAP, PAR, TRACE
–mppr			Implementation (with Multi-Pass Place and Route)	NGDBuild, MAP, PAR (multiple passes), TRACE
–tsim			Timing Simulation	NGDBuild, NetGen
–ecn			Equivalence Checking	NGDBuild, NetGen
–sta			Static Timing Analysis	NGDBuild, NetGen
–config			Configuration	BitGen
–synth	cpld.flw	CPLD	Synthesis	XST, Synplicity, Leonardo Spectrum
–fit			Fit	NGDBuild, CPLDfit, TAEngine, HPREP6
–tsim			Timing Simulation	TSim, NetGen
–synth	fsim.flw	FPGA/ CPLD	Synthesis	XST, Synplicity, Leonardo Spectrum
–fsim			Functional Simulation	NGDBuild, NetGen

Flow File Format

The flow file is an ASCII file that contains the following information:

Note: You can use variables for the file names listed on the Input, Triggers, Export, and Report lines. For example, if you specify Input: <design>.vhd on the Input line, XFLOW automatically reads the VHDL file in your working directory as the input file.

ExportDir

This section specifies the directory in which to copy the output files of the programs in the flow. The default directory is your working directory.

Note: You can also specify the export directory using the –ed command line option. The command line option overrides the ExportDir specified in the flow file.

ReportDir

This section specifies the directory in which to copy the report files generated by the programs in the flow. The default directory is your working directory.

Note: You can also specify the report directory using the –rd command line option. The command line option overrides the ReportDir specified in the flow file.

Global user-defined variables

This section allows you to specify a value for a global variable, as shown in the following example:

Variables

$simulation_output = time_sim;

End variables

The flow file contains a program block for each program in the flow. Each program block includes the following information:

Program program_name

This line identifies the name of the program block. It also identifies the command line executable if you use an executable name as the program_name, for example, ngdbuild. This is the first line of the program block.

Flag: ENABLED | DISABLED
ENABLED: This option instructs XFLOW to run the program if there are options in the options file.
DISABLED: This option instructs XFLOW to not run the program even if there are corresponding options in the options file.
Input: filename

This line lists the name of the input file for the program. For example, the NGDBuild program block might list design.edn.

Triggers:

This line lists any additional files that should be read by the program. For example, the NGDBuild program block might list design.ucf.

Exports:

This line lists the name of the file to export. For example, the NGDBuild program block might list design.ngd.

Reports:

This line lists the report files generated. For example, the NGDBuild program block might list design.bld.

Executable: executable_name

This line is optional. It allows you to create multiple program blocks for the same program. When creating multiple program blocks for the same program, you must enter a name other than the program name in the Program line (for example, enter post_map_trace, not trce). In the Executable line, you enter the name of the program as you would enter it on the command line (for example, trce).

For example, if you want to run TRACE after MAP and again after PAR, the program blocks for post-MAP TRACE and
post-PAR TRACE appear as follows:

Program post_map_trce

Flag: ENABLED;

Executable: trce;

Input: <design>_map.ncd;

Exports: <design>.twr, <design>.tsi;

End Program post_map_trce

Program post_par_trce

Flag: ENABLED;

Executable: trce;

Input: <design>.ncd;

Reports: <design>.twr, <design>.tsi;

End Program post_par_trce

Note: If your option file includes a corresponding program block, its Program line must match the Program line in the flow file (for example, post_map_trace).

End Program program_name

This line identifies the end of a program block. The program_name should be consistent with the program_name specified on the line that started the program block.

User Command Blocks

To run your own programs in the flow, you can add a “user command block” to the Flow File. The syntax for a user command block is the following:

UserCommand

      Cmdline: <user_cmdline>;

End UserCommand

Following is an example:

UserCommand

      Cmdline: “myscript.csh”;

End UserCommand

Note: You cannot use the asterisk (*) dollar sign ($) and parentheses ( ) characters as part of your command line command.