ROM16X1

16-Deep by 1-Wide ROM

Architectures Supported

ROM16X1
Spartan-II, Spartan-IIE	Primitive
Spartan-3	Primitive
Virtex, Virtex-E	Primitive
Virtex-II, Virtex-II Pro, Virtex-II Pro X	Primitive
XC9500, XC9500XV, XC9500XL	No
CoolRunner XPLA3	No
CoolRunner-II	No

ROM16X1 is a 16-word by 1-bit read-only memory. The data output (O) reflects the word selected by the 4-bit address (A3 – A0). The ROM is initialized to a known value during configuration with the INIT=value parameter. The value consists of four hexadecimal digits that are written into the ROM from the most-significant digit A=FH to the least-significant digit A=0H. For example, the INIT=10A7 parameter produces the data stream:

   0001 0000 1010 0111

An error occurs if the INIT=value is not specified. See the appropriate CAE tool interface user guide for details.

Usage

For HDL, the ROM16X1 design element should be instantiated rather than inferred.

VHDL Instantiation Template

   -- ROM16X1: 16 x 1 Asynchronous Distributed  => LUT ROM
   -- The current version of the Xilinx HDL Libraries Guide

   ROM16X1_inst : ROM16X1
   -- Edit the following generic to define the contents of the ROM.
   generic map (
      INIT => X"0000")
   port map (
      O => O,   -- ROM output
      A0 => A0, -- ROM address[0]
      A1 => A1, -- ROM address[1]
      A2 => A2, -- ROM address[2]
      A3 => A3  -- ROM address[3]
   );


   -- End of ROM16X1_inst instantiation

Verilog Instantiation Template

   ROM16X1 ROM16X1_inst (
      .O(O),   // ROM output
      .A0(A0), // ROM address[0]
      .A1(A1), // ROM address[1]
      .A2(A2), // ROM address[2]
      .A3(A3)  // ROM address[3]
   );

// Edit the following defparam to define the contents of the ROM.
// If the instance name to the ROM is changed, that change needs to
// be reflected in the defparam statements.

   defparam ROM16X1_inst.INIT = 16'h0000;


// End of ROM16X1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM