Chapter 3 FPGA Optimization This chapter contains the following sections: "Introduction" "Virtex Specific Synthesis Options" "Macro Generation" "Using DSP48 Block Resources" "Mapping Logic onto Block RAM" "Flip-Flop Retiming" "Incremental Synthesis Flow" "Speed Optimization Under Area Constraint" "Log File Analysis" "Implementation Constraints" "Virtex Primitive Support" "Cores Processing" "Specifying INITs and RLOCs in HDL Code" "PCI Flow"
This chapter contains the following sections:
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