Log File Analysis

The XST log file related to FPGA optimization contains the following sections.

Design optimization
Resource usage report
Timing report

Design Optimization

During design optimization, XST reports the following.

Potential removal of equivalent flip-flops

Two flip-flops (latches) are equivalent when they have the same data and control pins.

Register replication

Register replication is performed either for timing performance improvement or for satisfying MAX_FANOUT constraints. Register replication can be turned off using the REGISTER_DUPLICATION constraint.

Following is a portion of the log file.

Starting low level synthesis ...

Optimizing unit <down4cnt> ...

Optimizing unit <doc_readwrite> ...

 ...

Optimizing unit <doc> ...

Building and optimizing final netlist ...

The FF/Latch <doc_readwrite/state_D2> in Unit <doc> is equivalent to the following 2 FFs/Latches, which will be removed : <doc_readwrite/state_P2> <doc_readwrite/state_M2>
Register doc_reset_I_reset_out has been replicated 2 time(s)

Register wr_l has been replicated 2 time(s)

Resource Usage

In the Final Report, the Cell Usage section reports the count of all the primitives used in the design. These primitives are classified in the following groups:

BELS

This group contains all the logical cells that are basic elements of the Virtex technology, for example, LUTs, MUXCY, MUXF5, MUXF6, MUXF7, MUXF8.

Flip-flops and Latches

This group contains all the flip-flops and latches that are primitives of the Virtex technology, for example, FDR, FDRE, LD.

RAMS

This group contains all the RAMs.

SHIFTERS

This group contains all the shift registers that use the Virtex primitives. They are SRL16, SRL16_1, SRL16E, SRL16E_1, and SRLC*.

Tristates

This group contains all the tristate primitives, namely the BUFT.

Clock Buffers

This group contains all the clock buffers, namely BUFG, BUFGP, BUFGDLL.

IO Buffers

This group contains all the standard I/O buffers, except the clock buffer, namely IBUF, OBUF, IOBUF, OBUFT, IBUF_GTL ...

LOGICAL

This group contains all the logical cells primitives that are not basic elements, namely AND2, OR2, ...

OTHER

This group contains all the cells that have not been classified in the previous groups.

The following section is an example of an XST report for cell usage:

==================================================

...

Cell Usage :

# BELS                             : 70

#      LUT2                        : 34

#      LUT3                        : 3

#      LUT4                        : 34

# FlipFlops/Latches                : 9

#      FDC                         : 8

#      FDP                         : 1

# Clock Buffers                    : 1

#      BUFGP                       : 1

# IO Buffers                       : 24

#      IBUF                        : 16

#      OBUF                        : 8

==================================================

Device Utilization summary

Where XST estimates the number of slices, gives the number of flip-flops, IOBs, BRAMS, etc. This report is very close to the one produced by MAP.

Clock Information

A short table gives information about the number of clocks in the design, how each clock is buffered and how many loads it has.

Timing Report

At the end of the synthesis, XST reports the timing information for the design. The report shows the information for all four possible domains of a netlist: "register to register", "input to register", "register to outpad" and "inpad to outpad".

The following is an example of a timing report section in the XST log:

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal                       | Clock buffer(FF name)  | Load  |

-----------------------------------+------------------------+-------+

clk                                | BUFGP                  | 9     |

-----------------------------------+------------------------+-------+

Timing Summary:

---------------

Speed Grade: -6

   Minimum period: 7.523ns (Maximum Frequency: 132.926MHz)

   Minimum input arrival time before clock: 8.945ns

   Maximum output required time after clock: 14.220ns

   Maximum combinational path delay: 10.889ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

======================================================================

Timing constraint: Default period analysis for Clock 'clk'

  Clock period: 7.523ns (frequency: 132.926MHz)

  Total number of paths / destination ports: 63 / 22

----------------------------------------------------------------------

Delay:               7.523ns (Levels of Logic = 2)

  Source:            sdstate_FFD1

  Destination:       sdstate_FFD2

  Source Clock:      clk rising

  Destination Clock: clk rising

  Data Path: sdstate_FFD1 to sdstate_FFD2

                          Gate   Net

  Cell:in->out   fanout   Delay  Delay   Logical Name(NetName)

  ------------------------------------   ---------------------

  FDC:C->Q           15   1.372  2.970   state_FFD1 (state_FFD1)

  LUT3:I1->O         1    0.738  1.26    LUT_54 (N39)

  LUT3:I1->O         1    0.738  0.00    I_next_state_2 (N39)

  FDC:D                   0.440          state_FFD2

  ------------------------------------

  Total                   7.523ns (3.288ns logic, 4.235ns route)

                                  (43.7% logic, 56.3% route)

                          Gate   Net

  Cell:in->out   fanout   Delay  Delay   Logical Name (Net Name)

  ------------------------------------   ---------------------

  FDC:C->Q           15   1.372  2.970   I_state_2

  begin scope: 'block1'

  LUT3:I1->O          1   0.738  1.265   LUT_54

  end scope: 'block1'

  LUT3:I0->O          1   0.738  0.000   I_next_state_2

  FDC:D                   0.440          I_state_2

  ------------------------------------

  Total                          7.523ns

Timing Summary

The Timing Summary section gives a summary of the timing paths for all 4 domains:

The path from any clock to any clock in the design:

Minimum period: 7.523ns (Maximum Frequency: 132.926MHz)

The maximum path from all primary inputs to the sequential elements:

Minimum input arrival time before clock: 8.945ns

The maximum path from the sequential elements to all primary outputs:

Maximum output required time before clock: 14.220ns

The maximum path from inputs to outputs:

Maximum combinational path delay: 10.899ns

If there is no path in the domain concerned, "No path found" is then printed instead of the value.

Timing Detail

The Timing Detail section describes the most critical path in detail for each region:

The start point and end point of the path, the maximum delay of this path, and the slack. The start and end points can be: Clock (with the phase: rising/falling) or Port:

Path from Clock 'sysclk' rising to Clock 'sysclk' rising : 7.523ns (Slack: -7.523ns)

The detailed path shows the cell type, the input and output of this gate, the fanout at the output, the gate delay, the net delay estimated and the name of the instance. When entering a hierarchical block, begin scope is printed, and similarly end scope is printed when exiting a block.

The preceding report corresponds to the following schematic:

In addition, the Timing Report section shows the number of analyzed paths and ports. If XST is run with timing constraints, it displays the number of failed paths and ports as well. The number of analyzed and failed paths shows you how many timing problems there are in the design. The number of analyzed and failed ports may show you how they are spread in the design. The number of ports in a timing report represent the number of destination elements for a timing constraint.

For example, if you use the following timing constraints:

                 TIMESPEC "TSidentifier"=FROM "source_group" TO "dest_group" value units;

then the number of ports corresponds to the number of elements in the destination group.

For a given timing constraint, XST may report that the number of failed paths is 100. But the number of failed destination ports is only two flip-flops. This means that it is sufficient to only analyze the design description for these two flip-flops to detect what should be changed in order to meet timing.