Verilog Meta Comment Syntax

Constraints can be specified as follows in Verilog code:

// synthesis attribute AttributeName [of] ObjectName [is]      AttributeValue

Example:

// synthesis attribute RLOC of u123 is R11C1.S0

// synthesis attribute HU_SET u1 MY_SET

// synthesis attribute bufg of my_clock is "clk";

Note:  The parallel_case, full_case, translate_on and translate_off directives follow a different syntax described in "Verilog Meta Comments" in Chapter 7.