Variable Part Selects

Verilog 2001 adds the capability to use variables to select a group of bits from a vector. A variable part select is defined by the starting point of its range and the width of the vector, instead of being bounded by two explicit values. The starting point of the part select can vary, but the width of the part select remains constant.

+:   —Indicates that the part select increases from the starting point.
-:  —Indicates that the part select decreases from the starting point.

Example:

reg [3:0] data;

reg [3:0] select; // a value from 0 to 7

wire [7:0] byte = data[select +: 8];