Structural Verilog Features

Structural Verilog descriptions assemble several blocks of code and allow the introduction of hierarchy in a design. The basic concepts of hardware structure are the module, the port and the signal. The component is the building or basic block. A port is a component I/O connector. A signal corresponds to a wire between components.

In Verilog, a component is represented by a design module. The module declaration provides the "external" view of the component; it describes what can be seen from the outside, including the component ports. The module body provides an "internal" view; it describes the behavior or the structure of the component.

The connections between components are specified within component instantiation statements. These statements specify an instance of a component occurring within another component or the circuit. Each component instantiation statement is labeled with an identifier. Besides naming a component declared in a local component declaration, a component instantiation statement contains an association list (the parenthesized list) that specifies which actual signals or ports are associated with which local ports of the component declaration.

The Verilog language provides a large set of built-in logic gates which can be instantiated to build larger logic circuits. The set of logical functions described by the built-in gates includes AND, OR, XOR, NAND, NOR and NOT.

Here is an example of building a basic XOR function of two single bit inputs a and b.

module build_xor (a, b, c);

  input a, b;

  output c;

  wire c, a_not, b_not;

    not a_inv (a_not, a);

    not b_inv (b_not, b);

    and a1 (x, a_not, b);

    and a2 (y, b_not, a);

    or out (c, x, y);

endmodule

Each instance of the built-in modules has a unique instantiation name such as a_inv, b_inv, out. The wiring up of the gates describes an XOR gate in structural Verilog.

Example 7-11 gives the structural description of a half adder composed of four, 2 input nand modules.

Example 7-11 Structural Description of a Half Adder

module halfadd (X, Y, C, S);

  input X, Y;

  output C, S;

  wire S1, S2, S3;

  nand NANDA (S3, X, Y);

  nand NANDB (S1, X, S3);

  nand NANDC (S2, S3, Y);

  nand NANDD (S, S1, S2);

  assign C = S3;

endmodule

Figure 7-1: Synthesized Top Level Netlist

The structural features of Verilog HDL also allow you to design circuits by instantiating pre-defined primitives such as gates, registers and Xilinx® specific primitives like CLKDLL and BUFGs. These primitives are other than those included in the Verilog language. These pre-defined primitives are supplied with the XST Verilog libraries (unisim_comp.v).

Example 7-12 Structural Instantiation of Register and BUFG

module foo (sysclk, in, reset, out);

  input sysclk, in, reset;

  output out;

  reg out;

  wire sysclk_out;

  FDC register (sysclk, reset, in, out);  //position based referencing

  BUFG clk (.O(sysclk_out), .I(sysclk));  //name based referencing

  ...

endmodule

The unisim_comp.v library file supplied with XST, includes the definitions for FDC and BUFG.

module FDC ( C, CLR, D, Q);

  input C;

  input CLR;

  input D;

  output Q;

endmodule

// synthesis attribute BOX_TYPE of FDC is "BLACK_BOX"

module BUFG ( O, I);

  output O;

  input I;

endmodule

// synthesis attribute BOX_TYPE of BUFG is "BLACK_BOX"