Parameters

Verilog modules support defining constants known as parameters which can be passed to module instances to define circuits of arbitrary widths. Parameters form the basis of creating and using parameterized blocks in a design to achieve hierarchy and stimulate modular design techniques. The following is an example of the use of parameters. Null string parameters are not supported.

Example 7-13 Using Parameters

module lpm_reg (out, in, en, reset, clk);

  parameter SIZE = 1;

  input in, en, reset, clk;

  output out;

  wire [SIZE-1 : 0] in;

  reg  [SIZE-1 : 0] out;

always @(posedge clk or negedge reset)

  begin

    if (!reset)

      out <= 1’b0;

    else

      if (en)

        out <= in;

      else

        out <= out;    //redundant assignment

  end

endmodule

module top ();    //portlist left blank intentionally

  ...

  wire [7:0] sys_in, sys_out;

  wire sys_en, sys_reset, sysclk;

  lpm_reg #8 buf_373 (sys_out, sys_in, sys_en, sys_reset, sysclk);

  ...

endmodule

Instantiation of the module lpm_reg with a instantiation width of 8 causes the instance buf_373 to be 8 bits wide.