Verilog Limitations in XST

This section describes Verilog limitations in XST support for case sensitivity, and blocking and nonblocking assignments.

Case Sensitivity

XST supports case sensitivity as follows:

Designs can use case equivalent names for I/O ports, nets, regs and memories.
Equivalent names are renamed using a postfix ("rnm<Index>").
A rename construct is generated in the NGC file.
Designs can use Verilog identifiers that differ only in case. XST renames them using a postfix as with equivalent names.

Following is an example.

module upperlower4 (input1, INPUT1, output1, output2);

  input input1;

  input INPUT1;

For the above example, INPUT1 is renamed to INPUT1_rnm0.

The following restrictions apply for Verilog within XST:

Designs using equivalent names (named blocks, tasks, and functions) are rejected.

Example:

...

always @(clk)

begin: fir_main5

  reg [4:0] fir_main5_w1;

  reg [4:0] fir_main5_W1;

This code generates the following error message:

ERROR:Xst:863 - "design.v", line 6: Name conflict (<fir_main5/fir_main5_w1> and <fir_main5/fir_main5_W1>)

Designs using case equivalent module names are also rejected.

Example:

module UPPERLOWER10 (...);

...

module upperlower10 (...);

...

This example generates the following error message:

ERROR:Xst:909 - Module name conflict (UPPERLOWER10 and upperlower10).

Blocking and Nonblocking Assignments

XST rejects Verilog designs if a given signal is assigned through both blocking and nonblocking assignments as in the following example.

always @(in1)

begin

  if (in2)

    out1 = in1;

  else

    out1 <= in2;

end

If a variable is assigned in both a blocking and nonblocking assignment, the following error message is generated:

ERROR:Xst:880 - "design.v", line n: Cannot mix blocking and non blocking assignments on signal <out1>.

There are also restrictions when mixing blocking and nonblocking assignments on bits and slices.

The following example is rejected even if there is no real mixing of blocking and non blocking assignments:

if (in2)

  begin

    out1[0] = 1’b0;

    out1[1] <= in1;

  end

else

  begin

    out1[0] = in2;

    out1[1] <= 1’b1;

  end

Errors are checked at the signal level, not at the bit level.

If there is more than a single blocking/non blocking error, only the first one is reported.

In some cases, the line number for the error might be incorrect (as there might be multiple lines where the signal has been assigned).

Integer Handling

There are several cases where XST handles integers differently from other synthesis tools, and so they must be coded in a particular way.

In Case statements, do not use unsized integers in case item expressions, as this causes unpredictable results. In the following example, the case item expression "4" is an unsized integer that causes unpredictable results. To avoid problems, size the "4" to 3 bits as shown below.

reg [2:0] condition1;

always @(condition1)

  begin

    case(condition1)

      4    : data_out = 2;    // < will generate bad logic

      3'd4 : data_out = 2;    // < will work

    endcase

  end

In concatenations, do not use unsized integers, as this causes unpredictable results. If you must use an expression that results in an unsized integer, assign the expression to a temporary signal, and use the temporary signal in the concatenation as shown below.

reg [31:0] temp;

assign temp = 4'b1111 % 2;

assign dout = {12/3,temp,din};