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Verilog Language Support Tables
The following tables indicate which Verilog constructs are supported in XST. Previous sections in this chapter describe these constructs and their use within XST.
Note: XST does not allow underscores as the first character of signal names (for
example, _DATA_1).
Table 7-3: Constants Integer Constants Supported Real Constants Supported Strings Constants Unsupported
Table 7-6: Procedural Assignments Blocking Assignments Supported Non-Blocking Assignments Supported Continuous Procedural Assignments assign Supported with limitations See "Assign and Deassign Statements" deassign force Unsupported release Unsupported if Statement if, if else Supported case Statement case, casex, casez Supported forever Statement Unsupported repeat Statement Supported (repeat value must be constant) while Statement Supported for Statement Supported (bounds must be static) fork/join Statement Unsupported Timing Control on Procedural Assignments delay (#) Ignored event (@) Unsupported wait Unsupported named events Unsupported Sequential Blocks Supported Parallel Blocks Unsupported Specify Blocks Ignored initial Statement Supported always Statement Supported task Supported functions Supported (Constant Functions Unsupported) disable Statement Supported
Table 7-8: Design Hierarchy Module definition Supported Macromodule definition Unsupported Hierarchical names Unsupported defparam Supported Array of instances Supported
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