XPower

Creating VCD Files for Verilog

To Create VCD Files for Verilog

To generate a VCD file, add the following code to each Verilog test bench.

// The following code will generate a VCD file containing
// all of the nets in the instance t.uut. "t" is the module name of the
// testfixture, "uut" is the instance name
// of the design being tested.

initial begin
$dumpfile ("invchn26.vcd"); // Change filename as appropriate.
$dumpvars(1, t.uut);
end