XPower

Creating VCD Files for VHDL

To Create VCD Files for VHDL

For VHDL simulations, enter the commands to generate a VCD file interactively, or insert them in a do file.

vcd file my_design.vcd
vcd add testbench/uut/*

This technique works for both VHDL and Verilog in ModelSim™.

Notes

When creating a VCD file using the NC simulator, the command must include the -f switch.
The above lines generate a VCD file called my_design.vcd. The entity name of our test bench is testbench and the instance name of the unit under test is uut.
Using the -r switch with ModelSim's vcd add command, or specifying a number of levels other than 1 to the $dumpvars Verilog task, results in a large but significantly more accurate VCD file. Using the -r switch is highly recommended.
VCD files can grow quite large for larger designs, or even for smaller designs if the simulation run time is long enough. Using a VCD file to set the activity rates of signals in XPower may not be an efficient method for certain types of designs, such as watchdog timers.
XPower will read a VCD file only up until the first break in the simulation, or vcd off command. After this a warning message will be issued and all data following the vcd off or $dumpoff command in the VCD file will be ignored.