Platform Studio
The Xilinx® Platform Studio (XPS) main window consists of several viewing panels. The panel names are identified by number in the illustration below.
The Console Window acts as a console for output, warning, and error messages from XPS and from other tools invoked by XPS. Error, warning, and output messages are separated in tabbed windows. Click the Error and Warning links to open associated answer records. If you right-click or double-click an error that has an associated file name and line number, you can navigate to that file in the editor.
The Project Information Area has three tabs:
The Project tab opens the Project Explorer, which lists references to a variety of project-related files. These are grouped together in the following general categories:
Project Files — This category includes all project-specific files. These include the Microprocessor Hardware Specification (MHS) files, Microprocessor Software Specification (MSS) files, User Constraints File (UCF) files, iMPACT Command files, Implementation Option files, and Bitgen Option files. For more information on these files, refer to XPS Project Files.
Project Options — This category includes all project-specific options. The options include Device, Netlist, Implementation, HDL, and Sim Model. Double-click or right-click any entry to open the Project Options dialog box, in which you can change the option assignments.
Reference Files — This category includes all log and output files produced by the various XPS implementation processes. Double-click or right-click any entry to view a specific file in the XPS text editing window.
The Applications tab opens the Application Explorer. The Application Explorer lists all software application option setting, header files and source files associated with each application project. Double-click Add Software Application Project to create a new software application project. Each project must be associated with a processor in your hardware platform. You can find the currently selected processor displayed under the project tree. Right-click on the display to change the processor assignment.
Right-click a software application project entry to build, clean or delete the project. You can set the compiler option for the project or generate the linker script. You can also mark the project as the image to load the BRAM during device initialization.
To add an existing source or header files to the software application project, double-click Sources or Headers. In the Select Source/Header File to Add to Project dialog box, you can add new source or header files using the XPS text editor.
The IP Catalog tab opens the IP Catalog, which lists all the EDK IP cores, as well as any custom IP cores that you created. If a project is open, only the IP cores compatible with the target Xilinx device architecture are displayed. The catalog lists information about the IP cores, including release version, status (active, early access or deprecated), lock (not licensed, locked, or unlocked), processor support and a short description. Additional details about the IP core, including the version change history, data sheet, and Microprocessor Peripheral Description file (MPD), are available in the right-click menu. By default the IP cores are grouped by function.
The System Assembly View is always displayed when an XPS project is open, and it closes when the project is closed. This view allows you to view and edit your hardware platform. Select the Bus Interface, Ports, and Addresses filters to view the corresponding aspects of your design. The default is Hierarchical view, in which the information of your design is grouped into a tree by the IP core instances in your hardware platform. The Expand All Tree Nodes and Collapse All Tree Nodes tool bar buttons at the top of the pane allow you to expand and collapse all the nodes in the IP instance tree. You can also expand and collapse an individual tree node by clicking on the +/- sign next to it. The Flat View tool bar toggle button allows you to display the information with or without the IP core instance tree. In the flat view, you can sort the table alphanumerically by any column.
Note To tile the System Assembly view with another file open in the main window, use the tile buttons in the toolbar.
The Connectivity Panel is part of the System Assembly View when the Bus Interface filter is selected. This panel is a graphical representation of the bus connectivity of your hardware platform. Each vertical line represents a bus, and each horizontal line represents the bus interfaces for an IP core. A connector is displayed at the intersection if a compatible connection can be made between the bus and IP core bus interfaces. The lines and connectors are color-coded to show the compatibility. The different shapes of the connections symbolize the mastership of the IP core bus interface. A hollow connector represents a potential connection that you can make, and a filled connector represents a connection made. To make or disconnect a connection, click the connector symbol.
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