Platform Studio

Including an Embedded Submodule in Your Top-Level Design

In your top-level FPGA design, you must instantiate and connect the embedded processor system. You must also copy any design constraints generated by XPS into the User Constraints File (UCF) of your Xilinx® ISE™ project.

Instantiating the Embedded Submodule

ISE provides an HDL instantiation template file that represents a top-level design containing the embedded submodule. You can use this template to copy component declaration and instantiation sample into your top-level HDL design.

In Project Navigator, select your embedded processor source in the Sources for Synthesis/Implementation pane.
In the Processes, run the View HDL Instantiation Template to open the template in the Project Navigator editor pane.
Copy the component declaration for the embedded system (VHDL) and paste it into your top-level design architecture.
Copy the instantiation sample of the embedded system into your top-level design and provide net name connections as necessary.

Connecting the Embedded Submodule

You can connect output ports of your embedded submodule to output ports and to other loads in your top-level design. You can drive input ports of your embedded design from input ports or other logic in your top-level design.

Each tristate output port of your embedded submodule design is brought out as a data (portname_O) and active-low enable (portname_T) signal pair at the component interface. Normally, you should infer or instantiate a tristate buffer for each data/enable pair and connect its output to an output port of the top-level design.

Each bidirectional port of your embedded submodule is brought out as a data output (portname_O), active-low output enable (portname_T), and data input (portname_I) at the component interface. Normally, you should infer or instantiate a tristate buffer for each data output/enable pair, and connect its output and the submodule's data input port to a bidirectional port of the top-level design.

If you targeted a specific development board in the Base System Builder (BSB), you should use the same port names in your top-level design as BSB generated on the embedded submodule component. This facilitates the copying of pinout constraints.

Copying Constraints to Your ISE Project

Whenever you run the BSB in XPS, it generates a UCF file, projectname.ucf, located in the data subfolder of your XPS project. This UCF file contains a few basic timing constraints representing your selected processor reference clock frequency. If you have selected a specific development board in BSB, the UCF file also contains a complete pinout specification for the on-board peripherals you included in your design. The UCF might also include I/O constraints, such as IOSTANDARD, for some pins.

Copying BSB-Generated Constraints into an Existing UCF

If you already have a UCF source file added to your top-level ISE project, you can copy the BSB-generated constraints into it. If any embedded submodule ports referenced in the BSB-generated constraints connect to top-level ports of a different name, you must edit the net names in the constraints accordingly.

Alternatively, you can use the Constraints Editor available in ISE to import the pinout constraints from the BSB-generated UCF file into your ISE project constraints file. This works only if all the embedded submodule ports referenced in the BSB-generated pinout constraints connect to top-level ports of the same name.

In Project Navigator, select your top-level UCF source in the Sources for Synthesis/Implementation pane.
Run the Assign Package Pins process in the Processes pane.
In the editor window that appears, select File > Import.
Browse to the data subfolder in your XPS project area and open the UCF file. All top-level ports connected to BSB-generated embedded submodule ports inherit the BSB-generated I/O constraints.

Re-Using Your BSB-Generated UCF for Your Top-Level Design

If you do not already have a UCF file for your top-level design, you can add a copy of the BSB-generated UCF file to use as a starting point.

In Project Navigator, select Project > Add Copy of Source.
Browse and select the UCF in the data folder of your XPS project.
Associate the selected UCF file with the top-level module of your ISE project.

What to Do Next

If you have not already done so, begin developing your embedded software applications. Begin by assigning drivers, libraries, and operating systems.

If your embedded processor subsystem is complete, see Implement the FPGA design containing your submodule.