Platform Studio

Implementing the Hardware Platform

Overview

After completing hardware platform design entry, you are ready to:

Specify design constraints
Generate the bitstream (BIT) file that represents the completed hardware platform

To create the BIT file for downloading and implement the design, you must first set up your User Constraints File (UCF).

As in ISE™, an FPGA design implemented using EDK requires a UCF. Primarily, the UCF specifies pinouts and timing constraints. It can also control a variety of other hardware implementation features, such as the configurable electrical characteristics of your FPGA I/O signals.

Note If using ISE to implement your hardware design, use the Project Navigator editing tools to enter all constraints. This topic focuses on designing in the Xilinx® Platform Studio (XPS) environment.

If you are implementing an FPGA design consisting of an embedded processor exclusively, and if you are using only XPS, you must provide a certain minimum set of constraints before invoking the Generate Bitstream command in XPS.

If you used the Base System Builder (BSB) Wizard to create your initial hardware platform, it will have generated a UCF in the data folder of your XPS project. The UCF contains a few basic timing constraints that represent your selected processor reference clock frequency.

If you selected a specific development board in BSB, the UCF file also contains a complete pinout specification for connections to the on-board peripherals you specified for your design. You should not have to modify the BSB-generated pinout if you are downloading to the targeted development board. You can add other constraints.

If you did not target a specific development board using BSB, you can either provide a complete pinout in the UCF file or let the place-and-route tools select pin locations for you.

Setting up Your User Constraints File

To access the UCF file for your XPS project:

Click the Project tab in the Project Information Area of the main window and look for the UCF file under the Project Files heading.
Double-click the UCF file to open it in the System Assembly Panel.

The UCF should have the same base filename as the project (XMP) file, and it must reside in the data subfolder of your project directory.

Specifying Pin Constraints

You must often provide an LOC (Location) constraint to define the FPGA pin location for each external port. To view the list of the external ports, do the following:

In the XPS main window, click the System Assembly tab.
Select the Ports filter.

LOC constraints take the following form:

Syntax:

NET port_name LOC=pin_number;

Example:

NET RS232_RX_pin LOC=U4;

Specifying Timing Constraints

For typical embedded processor designs, you only need to specify the input (reference) clock period to ensure that your system meets performance requirements. In some cases, your design might contain off-chip peripherals, such as memory controllers, that have particular input and output timing requirements. You should also declare Timing IGnore (TIG) constraints on signals that are not timing critical to allow better place and route tools to optimize other timing paths. The following are typical of the basic timing constraints you must provide in your UCF file:

Syntax:

Net clock_port PERIOD = value;

Net reset_port TIG;

Example:

Net sys_clk_pin PERIOD = 20000 ps;

Net sys_rst_pin TIG;

Generating the Hardware Platform

Hardware generation consists of generating the netlist and generating the bitstream.

Generating the Netlist

Select Hardware > Generate Netlist. This calls the platform building tool, Platgen, which does the following:

Reads the design platform configuration Microprocessor Hardware Specification (MHS) file
Generates a VHDL representation
Runs the XST synthesis tool
Produces the netlist file in Xilinx NGC format

Generating the Bitstream

Select Hardware > Generate Bitstream. If necessary, this runs Platgen to produce the netlist (described above). It then runs the ISE implementation tools, which read the UCF file and produce the BIT file containing your hardware design. Software patterns, if any, are not included.

What to Do Next

Add software platform design elements

Begin assigning drivers, libraries, and operating systems