Platform Studio
The EDK system has several project file types. You can edit some of these files according to your design needs.
A Xilinx® Microprocessor Project (XMP) file is the top-level project file for an EDK design. This file is used for project management, and you should not attempt to edit it.
The BSB file is the playback file generated by the Base System Builder. You can use it to create new projects with pre-defined options.
The Black Box Definition (BBD) file manages the file locations of optimized hardware netlists for the black-box sections of your peripheral design.
A Microprocessor Driver Description (MDD) file contains directives for customizing software drivers.
The Microprocessor Hardware Specification (MHS) file defines the hardware component. The MHS file serves as an input to the Platform Generator (Platgen) tool. An MHS file defines the configuration of the embedded processor system, and includes the following:
Bus architecture
Peripherals
Processor
System Connectivity
Address space
A Microprocessor Library Definition (MLD) file contains directives for customizing software libraries and generating Board Support Packages (BSP) for operating systems (OS).
Microprocessor Peripheral Definition (MPD) file defines the interface for the peripheral. An MPD file has the following characteristics:
Lists ports and default connectivity for bus interfaces
Lists parameters and default values
Any MPD parameter is overwritten by the equivalent MHS assignment.
The Microprocessor Software Specification (MSS) is used as an input file to the Library Generator (Libgen). The MSS file contains directives for customizing operating systems (OS), libraries, and drivers.
A Peripheral Analyze Order (PAO) file contains a list of HDL files that are needed for synthesis, and defines the analyze order for compilation.
The User Constraints File (UCF) specifies timing and placement constraints for the FPGA Design.
Options to the Bitstream generation tool.
A script file used for downloading bitstreams using IMPACT.
The design implementation command line options to the ISE implementation tools such as Map and Par.
A Block Memory Map (BMM) file is a text file that has syntactic descriptions of how individual Block RAMs constitute a contiguous logical data space. When updating the FPGA bitstream with memory initialization data (typically the executable program), the Data2Mem utility uses the BMM file to direct the translation of data into the proper initialization form. Although the BMM file is a text file direct editing is not recommended. This file is generated by the Platform Generator (Platgen) and updated with physical location information by the Bitstream Generator tool (Bitgen). Refer to the Embedded System Tools Reference Manual for more information.
Electronic Data Interchange Format (EDIF) is an industry standard file format for specifying a design netlist.
The Executable and Linkable Format (ELF) is a common standard in computing. An executable or executable file, in computer science, is a file whose contents are meant to be interpreted as a program by a computer. Most often, they contain the binary representation of machine instructions of a specific processor, but can also contain an intermediate form that requires the services of an interpreter to be run.
The Microprocessor Hardware Specification (MHS) file defines the hardware component. The MHS file is serves as an input to the Platform Generator (Platgen) tool. An MHS file defines the configuration of the embedded processor system, and includes the following:
Bus architecture
Peripherals
Processor
System connectivity
Address space
A Microprocessor Software Specification (MSS) file serves as an input to the Library Generator (Libgen). The MSS file contains directives for customizing operating systems (OS), libraries, and drivers.
The NGC file is a netlist that contains both logical design data and constraints. This file replaces both EDIF and NCF files.
See Also
Platform Format Specification Reference Manual
Send any feedback on this topic to isedocs@xilinx.com.
Copyright © 1995-2005 Xilinx, Inc. All rights reserved.