Implementation Overview for FPGAs

After synthesis, you run design implementation, which comprises the following steps:

Translate, which merges the incoming netlists and constraints into a Xilinx® design file
Map, which fits the design into the available resources on the target device
Place and Route, which places and routes the design to the timing constraints
Programming file generation, which creates a bitstream file that can be downloaded to the device

In the Sources tab, select Synthesis/Implementation from the Design View drop-down list, and select the top module . In the Processes tab, double-click Implement Design to run the implementation process in one step, or double-click Translate, Map, and Place & Route to run each of the implementation steps separately. To generate the programming file, double-click Generate Programming File. Alternatively, you can select Process > Implement Top Module to run Implement Design on the top module. For details, see Implementing the Top Module.

Default property values are used for the implementation process, unless you modify them. Properties can be set for the Implement Design process or for each of the separate implementation processes.

Note In addition to the regular implementation flow described here, you can use other design re-use strategies. For more details, see Using Partitions and Using SmartGuide.

Translate

The Translate process merges all of the input netlists and design constraints and outputs a Xilinx native generic database (NGD) file, which describes the logical design reduced to Xilinx primitives. See the following table for details.

Translate Process
Command line tool	NGDBuild
Input files	EDIF, SEDIF, EDN, EDF, NGC, UCF, NCF, URF, NMC, BMM
Output files	BLD (report), NGD
Process properties	Translate Properties
Tools available after running process	Constraints Editor, Floorplan Editor, Floorplanner, PACE Note Each of these tools modifies the UCF file. When you rerun Translate with the updated UCF, the NGD file is updated.

Map

The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs. The output design is a native circuit description (NCD) file that physically represents the design mapped to the components in the Xilinx FPGA. See the following table for details.

Map Process
Command line tools	MAP
Input files	NGD, NMC, NCD, NGM Note The NCD and NGM files are for guiding.
Output files	NCD, PCF, NGM, MRP (report), GRF
Process Properties	Map Properties
Tools available after running process	Floorplanner, FPGA Editor, Timing Analyzer

Place and Route

The Place and Route process takes a mapped NCD file, places and routes the design, and produces an NCD file that is used as input for bitstream generation. See the following table for details.

Place and Route Process
Command line tools	PAR
Input files	NCD, PCF Note In addition to the NCD file from MAP, PAR also accepts an NCD file for guiding.
Output files	NCD, PAR (report), PAD, CSV, TXT, GRF, DLY
Process Properties	Place & Route Properties
Tools available after running process	Floorplanner, FPGA Editor, Timing Analyzer, XPower

Programming File Generation

The Generate Programming File process produces a bitstream for Xilinx device configuration. After the design is completely routed, you must configure the device so it can execute the desired function. See the following table for details.

Generate Programming File Process
Command line tools	BitGen
Input files	NCD, PCF, NKY
Output files	BGN, BIN, BIT, DRC, ISC, LL, MSD, MSK, NKY, ISC, RBA, RBB, RBD, RBT
Process Properties	General Options, Configuration Options, Startup Options, Readback Options, Encryption Options
Tools available after running process	iMPACT