Using Synplify or Synplify Pro for Synthesis

You can use the Synplify® or Synplify Pro® synthesis software from Synplicity®, Inc., to synthesize VHDL, Verilog, and mixed language designs into EDIF netlists. For detailed information, including how to get the best results, please refer to the documentation from the standalone Synplify or Synplify Pro software or from the Synplicity website at http://www.synplicity.com.

The ISE™ software works with the latest Synplify and Synplify Pro software. When invoked from the ISE software, the Synplify and Synplify Pro software run in batch mode for both floating and node-locked licenses. You can also run the Synplify or Synplify Pro software in standalone mode outside of the ISE environment. The Synplify and Synplify Pro software supports all Xilinx® device families.

Note If you run the Synplify or Synplify Pro software in standalone mode, any changes that you make to your project are not imported back into your ISE project.

What to Do First

Install the Synplify or Synplify Pro software.

Note These tools are not provided with the ISE software. Xilinx provides integration with the Synplicity software when both ISE software and Synplify or Synplify Pro software are installed. If you installed a synthesis tool but it does not appear as an option, set the path to the synthesis software in the Integrated Tools Options page of the Preferences dialog box.

In Project Navigator, do one of the following:

Create a project, selecting Synplify or Synplify Pro as your synthesis tool, as described in Creating a Project.
If you have an existing project, change the synthesis tool to Synplify or Synplify Pro, as described in Changing Project, Source, and Snapshot Properties.

To Use Synplify or Synplify Pro for Synthesis

In the Sources tab, select Synthesis/Implementation from the Design View drop-down list.
Select the top module .
In the Processes tab, double-click Synthesize - Synplify or Synthesize - Synplify Pro.

What to Expect

The Synplify tools run the Synthesize process and all preceding processes. The resulting EDIF file is placed in your project directory.

Properties

Default property values are used for the Synthesize process unless you modify them. You can set the following properties in the Process Properties dialog box:

What to Do Next

You can perform any of the following:

View the Synthesis Report.
View a register transfer level (RTL) schematic representation of your design.
View a technology schematic representation of your design.
Run the Implement Design process.