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XST Synthesis Overview

After design entry and optional simulation, you run synthesis. In the Sources tab, select Synthesis/Implementation from the Design View drop-down list, and select the top module . In the Processes tab, double-click Synthesize.

The ISE™ software includes Xilinx® Synthesis Technology (XST), which synthesizes VHDL, Verilog, or mixed language designs to create Xilinx-specific netlist files known as NGC files. Unlike output from other vendors, which consists of an EDIF file with an associated NCF file, NGC files contain both logical design data and constraints. XST places the NGC file in your project directory and the file is accepted as input to the Translate (NGDBuild) step of the Implement Design process. To specify XST as your synthesis tool, you must set the Synthesis Tool Project Property to XST, as described in Changing Project, Source, and Snapshot Properties. For details on using XST, see the XST User Guide.

Note You can set the Synthesis Tool to XST or to a partner synthesis tool. For details on using partner tools, see Using Synplify or Synplify Pro for Synthesis, or Using Precision for Synthesis.

XST Design Flow Overview

The following figure shows the flow of files through the XST software.

XST Input and Output Files

XST supports extensive VHDL and Verilog subsets from the following standards:

VHDL: IEEE 1076-1987, IEEE 1076-1993, including IEEE standard and Synopsys®

Verilog: IEEE 1364-1995, IEEE 1364-2001

In addition to a VHDL or Verilog design description, XST can also accept the following files as input:

Xilinx constraints file in which you can specify synthesis, timing, and specific implementation constraints that can be propagated to the NGC file.

Core files

These files can be in either NGC or EDIF format. XST does not modify cores. It uses them to inform area and timing optimization.

Note Cores are supported for FPGAs only, not CPLDs.

In addition to NGC files, XST also generates the following files as output:

Synthesis Report

This report contains the results from the synthesis run, including area and timing estimation. For details, see Viewing a Synthesis Report.

RTL schematic

This is a schematic representation of the pre-optimized design shown at the Register Transfer Level (RTL). This representation is in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, and is generated after the HDL synthesis phase of the synthesis process. Viewing this schematic may help you discover design issues early in the design process. For details, see Viewing an RTL Schematic - XST.

Technology schematic

This is a schematic representation of an NGC file shown in terms of logic elements optimized to the target architecture or "technology," for example, in terms of LUTs, carry logic, I/O buffers, and other technology-specific components. It is generated after the optimization and technology targeting phase of the synthesis process. Viewing this schematic allows you to see a technology-level representation of your HDL optimized for a specific Xilinx architecture, which may help you discover design issues early in the design process. For details, see Viewing a Technology Schematic - XST.

Note When the design is run in Incremental Synthesis mode, XST generates multiple NGC and NGR files, which each represent a single user design partition.

XST Detailed Design Flow

The following figure shows each of the steps that take place during XST synthesis. The following sections describe each step in detail.

HDL Parsing

During HDL parsing, XST checks whether your HDL code is correct and reports any syntax errors.

HDL Synthesis

During HDL synthesis, XST analyzes the HDL code and attempts to infer specific design building blocks or macros (such as MUXes, RAMs, adders, and subtracters) for which it can create efficient technology implementations. To reduce the amount of inferred macros, XST performs a resource sharing check. This usually leads to a reduction of the area as well as an increase in the clock frequency.

Finite state machine (FSM) recognition is also part of the HDL synthesis step. XST recognizes FSMs independent of the modeling style used. To create the most efficient implementation, XST uses the target optimization goal, whether area or speed, to determine which of several FSM encoding algorithms to use.

You can control the HDL synthesis step using constraints. You can enter constraints using any of the following methods:

HDL source file

Enter VHDL attributes or Verilog metacomments.

Enter global parameters and module-level constraints in the Xilinx constraints (XCF) file. See the "Design Constraints" chapter of the XST User Guide for more information on the use of constraints in the XCF file.

Project Navigator Process Properties

Set global parameters, such as the optimization goal or effort level. You can modify the synthesis properties in the following tabs of the Synthesize Process Properties dialog box:

Default property values are used for the Synthesize process, unless you modify them.

Note For more information on entering constraints, see Constraints Entry Methods.

Low Level Optimization

During low level optimization, XST transforms inferred macros and general glue logic into a technology-specific implementation. The flows for FPGAs and CPLDs differ significantly at this stage as follows:

Note For a list of supported FPGAs and CPLDs, see Architecture Support.

FPGA Flow

The FPGA flow is timing-driven and can be controlled using constraints, such as PERIOD and OFFSET. During low level optimization, XST infers specific components, such as the following:

Carry logic (MUXCY, XORCY, MULT_AND)
RAM (block or distributed)
Shift Register LUTs (SRL16, SRL16E, SRLC16, SRLC16E)
Clock Buffers (IBUFG, BUFGP)
Multiplexers (MUXF5, MUXF6, MUXF7, MUXF8)

The use of technology-specific features may come from a macro implementation mechanism or from general logic mapping. Due to mapping complexity issues, not all available FPGA features may be used. The FPGA synthesis flow supports advanced design and optimization techniques, such as Register Balancing and Incremental Synthesis.

Note For information on Register Balancing, see the "Design Constraints" chapter of the XST User Guide; for information on Incremental Synthesis, see the "Incremental Synthesis" section in the "FPGA Optimization" chapter. For information on specific components, see the Libraries Guides, available from the ISE Software Manuals collection.

CPLD Flow

The CPLD flow is not timing driven. You cannot specify the frequency of a clock or of an offset value. The goal of the CPLD flow is to reduce the number of logic levels. During low level optimization, XST generates a netlist that contains elements such as AND and OR gates. The CPLD Fitter then determines how to fit these equations to the targeted device. XST supports a special optimization mode, called Equation Shaping, in which XST optimizes and reduces the Boolean equations to sizes accepted by device macrocells. This forces the CPLD Fitter to retain the equation modifications through the KEEP and COLLAPSE constraints in the NGC file.

Note Equation Shaping only applies to CPLDs. For information on Equation Shaping, see the "CPLD Optimization" chapter of the XST User Guide.