Monitoring Hardware Signals

You can configure the parameters of an existing ChipScope core for hardware debugging. Additionally, you can click Add ChipScope Peripheral to instantiate a new ChipScope core for the following tasks:

Monitoring On-chip Peripheral Bus (OPB) signals (adding OPB Integrated Bus Analyzer (IBA))
Monitoring Processor Local Bus (PLB) signals (adding PLB IBA)
Monitoring arbitrary system level signals (adding Integrated Logic Analyzer (ILA))
Providing JTAG-based virtual input and output (VIO)

The options in the Basic tab can create a working system with the debug features facilitated. The settings in the Advanced tab provide more options for assigning values to the ChipScope core parameters.

The basic settings for each core are described below.

OPB IBA and PLB IBA

OPB IBA and PLB IBA ChipScope cores are added to monitor the OPB bus and PLB bus signals, respectively.

From the Monitor Bus Signals drop-down list, select the bus for which you want to monitor signals.
Select the signals that need to be monitored by selecting the corresponding checkbox.
If you want to have a co-debug between GNU Debugger (GDB) and ChipScope Analyzer, select the Enable Hardware/Software Co-debug check box and select the processor to use from the drop-down list.

You can also specify the number of signal samples that are to be collected. Since the collected samples are stored in the block RAM (BRAM), more samples collected increase the BRAM resource use. The total BRAM use by ChipScope cores is displayed in the Console window.

Hardware and software co-debugging does three things:

Connects IBA trig_out to processor stop signal so that the IBA can place the processor in the debug Halt mode.
Connect processor halted signal to IBA trig_in so that the halting of the processor can trigger the IBA to record samples.
Connect processor instruction signal to IBA trig_in so that the IBA can record the sequence of instructions. Do this only when the processor and bus operate at the same clock frequency.

As a result, the application running on the selected processor could trigger the ChipScope Analyzer to collect the signal waveforms for the signals being monitored. On the other hand, the ChipScope IBA core, when seeing a signal pattern, puts the processor in debug Halt mode. The IBA can also collect the hexadecimal signals of the running instructions.

Note For PowerPC, two bits of zero are attached to the end of this signal for better readability of the program count.

ILA

The ChipScope ILA is the most versatile ChipScope core, and can be used to monitor any signals in the design.

The available ports on the instance are displayed in the Available Ports on Instance window. The ILA port that is used to monitor the signals can be selected in the Signals Monitored by drop-down box. You must use the ILA ports in a sequential order. That is, the lower number of the port (such as TRIG0) must be used before you can use the higher number of port (such as TRIG1). Click Add to add the port as a signal to be monitored. As a result, the added signals are concatenated and connected to the selected port of the ILA core. You can specify the total number of 256 bits of signal to be monitored.

The clock used to monitor the signal should be equal to or faster than the frequency that the signal is operating at. Otherwise, the signals collected by ILA will be interleaved due to the slow clock.

VIO

The ChipScope VIO core supports asynchronous or synchronous input or output probes into the hardware. This core is not used like a logic analyzer to collect a signal trace, but to directly read and write logic signals at runtime from ChipScope Analyzer.

This tool supports only asynchronous VIO.

To monitor a signal as ChipScope Virtual Input, add it to the list of signals to be displayed. The signal is connected the asynch_out port of the VIO core.

To control a signal as ChipScope Virtual Output, add it to the list of signals to be controlled. The signal is connected to the asynch_in port of the VIO core.

To control a signal, the existing connection on that port might need to be disconnected in the Microprocessor Hardware Specification (MHS) file. The older connection is commented out and the new connection is added.

What to Do Next

After the debug configuration is done, use ChipScope Analyzer to monitor the hardware signals. The following flow is a typical flow for debugging with ChipScope Analyzer.

Generate a bit stream in XPS, as described in Generate Bitstream Command.
Configure the FPGA with the bitstream, as described in Downloading Bitstreams to an FPGA.
Launch Chipscope Analyzer software on your PC. Make sure that the PC is connected to the FPGA board through the parallel cable and JTAG.

The next steps are done in ChipScope Analyzer.

Select JTAG Chain > Xilinx Parallel Cable to connect to the FPGA board.
Select File > Import to import the signal name form .cdc file, which is located in <Project_Dir>/implementation/<corename>_wrapper/
Set up the trigger condition and waveform signals.
Select Trigger Setup > Run and wait for the triggers.

When the trigger condition is met, the monitored signals are recorded and wave forms are generated. If the Enable Hardware/Software Co-debug check box is enabled, you can also set a breakpoint in the software to trigger the ChipScope core to record the data and wave form.