This file describes the new features in the Xilinx® Integrated Software Environment (ISE™) 9.1i software release. It contains the following sections:
Following are the new devices, power analysis, and optimizations supported in this release:
This release supports the new Spartan™- 3A, Spartan™-3AN, and Virtex™-5 LXT devices.
Following are the new features in this release:
SmartGuide minimizes implementation differences between two versions of the same design. Faster runtimes will be realized, especially for small design changes. Timing will be preserved whenever possible. SmartGuide is available with Virtex™-5, Virtex™-4, Virtex™-II/II Pro, and all Spartan™-3 devices.
Improved quality for preserve=routing Partitions setting. Unroutes situations will not occur on designs using this setting. Partitions are available with Virtex™-5, Virtex™-4, Virtex™-2/2P, and all Spartan™-3 devices.
Runtime improvements for designs with tight constraints when the constraints are met.
Pause/Resume PAR using SmartPreview. Save intermediate results, view state of design (paths that fail timing, routing status). Allows bitstream generation and timing analysis.
Enhanced Design Rule Checking (DRC) warns users about partially locked buses with multiple I/O standards.
The following improvements are available for designs targeting, Virtex™- 4, Virtex™-5, and Spartan™-3A devices:
Project-aware Timing Improvement Wizard. Knows the project settings so the wizard does not suggest a previously used strategy.
Timing Analyzer Constraints are optimized in a tree-based layout.
Physical optimizations (map -timing, global optimization, and logic optimization): Enhanced stability and better Quality of Results.
Integration of PACE, Timing Analyzer, Constraints Editor, Floorplan view; also cross probing between those views and Design Summary.
Power Analysis support added for Virtex™-5 LX and Spartan™-3E devices.
Introduction of power optimization during XST synthesis.
Power optimization at Implementation level for Spartan™-3, Virtex™-4, and Virtex™-5 devices.
Source code control compatibility. Identifies files needed to recreate a result; allows import/export sources for source control; allow generation of ASCII representation of the project file, in the form of a Tcl script that can be used to regenerate the project with the same sources and setting.
Tcl command-line interface provides compatibility between batch/command-line and GUI usage.
Option to select Preferred Language in the case of mixed language projects.
More CORE Generator Cores now supported in ISE's Project Navigator: CORE Generator cores which output source code are now supported by ISE's Project Navigator.
Increased set of Tcl commands available for building a design using Partitions.
A complete list of the new features in XST 9.1i can be found at the beginning of the XST User Guide, available from the Software Manuals collection.
Partition Resource Reporting
XST now reports per-partition resource information. Designers do not have to run a full implementation to find out how many resources are estimated per Partition.
HDL Language
Introduce support of Constant Functions (Verilog-2001).
Introduce a possibility redefine generics (VHDL), parameters (Verilog) values and Verilog macros via ISE Synthesis Properties.
Power Optimization
Introduce Power optimization flow.
Macro Inference
Support inference for Multi-Core DSPs (MDSP) block of Spartan™-3A family: all DSP based macros supported on Virtex™-4 and Virtex™-5 architectures are supported on MDSP.
Introduced possibility to automatically replace Asynchronous Set/Reset signals with Synchronous signals throughout the entire design. This allows absorption of registers by DSP48 and BRAMs, improving quality of results.
Improved synthesis engine for filters.
Sequential Complex Multipliers support.
Improved Adders processing on DSP blocks (when the adder is not a part of a filter):
Introduced automatic BRAM resource management and possibility to pack 2 single-port BRAMs in a single BRAM primitive.
New inference capabilities: BRAMs with byte write enable, simple dual-port BRAM mode for Virtex™-5, and dual-port BRAMs.
Naming Conventions: XST has modified its internal signal names in order to improve signal name predictability.
ISE Simulator Update
Support for PowerPC, MGT, PCI-Express, and EtherMac hard IP blocks.
Differential signal support
GoTo Time feature
Ability to move cursor to next/previous transition.
Markers enhancements: ability to label markers, GoTo specific marker.
Improved search/find capabilities: find name in waveform viewer and hierarchy browser.
Name sorting in wave editor and wave viewer.
Ability to divide wave area into multiple panes via adding dividers.
Ability to display hierarchy information and signal value in text editor via tooltip.
Ability to create self-checking test bench.
Increased set of Tcl commands.
MXE is updated to ModelSim Xilinx® Edition III Version 6.2c.
New intuitive GUI for Compxlib to compile libraries for Modelsim PE/SE, NCSIM, and VCS.
Architecture Wizard Virtex-5 Support
New System Monitor Wizard
Clocking Wizard including: PLL to DCM configuration, DCM to PLL configuration, and PLL jitter support.
Ability to assign a constant value to a bus.
Up to 2 times faster rendering times for larger netlists.
Tcl language color coding.
Automatic code completion, using Ctrl+Enter key combination.
New optional black background color.
A preliminary Map report providing device usage statistics is now available prior to Timing-driven Packing and Placement (map -timing).
Links directly to answer records available from message list views.
Printing enabled for list and table views.
Message filtering controls dialog available from message list views.
Partitions report contains synthesis information.
A new Map log file is available.
Timing-driven Packing and Placement can perform optimizations to reduce overall power consumption.
A preliminary version of the Map report is written prior to Timing-driven Packing and Placement, so device usage statistics can be examined.
A new Map log file is available.
Improved Device Configuration Integration: iMPACT has been integrated as a view inside of ISE's Project Navigator. Now you can easily manage your configuration solutions without having to leave the Project Navigator environment.
Data Now Easily Placed in PROM Files: iMPACT and PromGen now allow ELF and MEM formatted data-files to be added into PROM files.
JTAG support for programming SPI PROMs.
WebTalk allows Xilinx to receive design statistics that will help us design future product that continue to meet our customer's needs.
Improved interface for sending statistics to Xilinx.
For Technical Support Issues, please visit www.xilinx.com/support where features such as the Answers Browser, Problem Solvers, and Users Forums may help to resolve your issue. If your issue can not be resolved on the support site, a WebCase can be created and a Technical Support engineer can further assist you. What's New on www.xilinx.com.