Our LogiCORE™ Initiator/Target for PCI™ cores are fully verified using our industry-proven test bench that simulates over six million unique PCI cycles. We also characterize our Initiator/Target cores together with our FPGAs to verify not only maximum timing, but also minimum and hold timing. Then, when we know that the timing constraints are met, we apply our unique Smart-IP™ technology to ensure that you achieve the same timing and functionality every time you implement the core. Thanks to our regular FPGA architecture with segmented routing using a modular core architecture, where the FIFOs, DMA channels, and the unique back-end logic de-coupled from the core, your design will not affect the PCI interface timing.