Virtex-6 HXT FPGA ML630 Evaluation Kit for OTN

Product Details

• Board Accessories

Documentation

• ML630 Documentation

Device Family Support

• Virtex-6 HXT

The Xilinx Virtex®-6 HXT FPGA ML630 Evaluation Kit for OTN provides developers with a cost-effective development platform to address 100GE and ODU-4 bandwidth-driven demands today. Based on the Virtex-6 HXT family, the industry’s first optically compliant programmable devices with superior transceiver performance, the comprehensive kit speeds time to revenue for next generation transponder, muxponder and ODU switching applications with proven reference designs and trial-use access licenses OTN Solutions IP suites and Ethernet Connectivity suites.

What's Included

Boards

• ML630 Base Board including an optically compliant Virtex-6 HXT FPGA
• Two HiTech Global CFP carrier cards (one with default 156.25MHz clock and one with default 174.7 MHz clock)
• Two HiTech Global Loopback module

Tools & IP

• ISE® Design Suite: Logic Edition Device-locked to the Virtex-6 HX565T FPGA

Example Design(s) and Demo(s)

• IBERT Reference Design

Documentation

• Hardware Users Guide (Available Online)
• IBERT Tutorial (Available Online)

Cables & Adapters

• Power Supplies (2)
• USB cable

Additional Materials

• Compact Flash Card

Key Features

• Two Virtex-6 XC6VHX565T-FFG1924C FPGAs U1 and U2
• On-board power regulators for all necessary voltages with power status LEDs
• Two types of external power supply jacks (12V “brick” DIN4 type, PC ATX type)
• USB JTAG configuration port for use with USB A-to-Mini-B cable
• System ACE™ controller with companion CompactFlash socket
• General purpose push button and DIP switches, LEDs, and test I/O header for each FPGA
• VGA 2X5 male debug header for each FPGA
• USB-to-UART bridge with USB Mini-B pcb connector for each FPGA
• Two VITA 57.1 FMC HPC connectors
• I2C bus hosting EEPROM, clock sources and FMC connectors
• A separate SiTime fixed 200 MHz 2.5V LVDS oscillator wired to each FPGAs global clock inputs
• Eight pairs of differential clock input SMA connectors
• Six I2C programmable Silicon Labs Si570 3.3V LVPECL 10 MHz-to-810 MHz oscillators
• Two differential input 8X8 cross-point switches providing 16 selectable differential clock sources
• Four sets of plug and receptacle FCI Airmax 120 pin connectors implementing the Interlaken interconnect protocol
• Six MGTX-to-MGTX (four TX/RX channels each) connections between FPGA U1 and FPGA U2
• Eighty LVDS pairs connected between FPGA U1 and FPGA U2