Virtex-6 HXT FPGA ML631 Evaluation Kit for PP/TM

Product Details

• Board Accessories

Documentation

• ML631 Documentation

Device Family Support

• Virtex-6 HXT

The Xilinx Virtex®-6 HXT FPGA ML631 Evaluation Kit for Packet Processing (PP) and Traffic Management (TM)  provides a comprehensive  development platform for 100G bandwidth-driven applications. Based on the Virtex-6 HXT family with superior transceiver performance, the kit speeds time to revenue for next generation of Packet Processing and Traffic management (PP/TM) applications. The Virtex-6 HXT FPGA  ML631 Evaluation Kit for PP/TM also protects investments in IP, and aligns migration paths for an optimized total development solution. Leveraging from the unified architecture, Virtex-6 FPGAs put designs on a smooth path to the Xilinx 7 series FPGAs for even higher integration.

What's Included

Boards

• ML631 Base Board including an optically compliant Virtex-6 HXT FPGA
• HiTech Global CFP carrier card
• HiTech Global Loopback module

Tools & IP

• ISE® Design Suite: Logic Edition Device-locked to the Virtex-6 HX565T FPGA

Example Design(s) and Demo(s)

• IBERT Reference Design

Documentation

• Hardware Users Guide (Available Online)
• IBERT Tutorial (Available Online)

Cables & Adapters

• Power Supplies (2)
• USB cable

Additional Materials

• Compact Flash Card

Key Features

• Two Virtex-6 XC6VHX565T-2FFG1923C FPGAs U1 and U2
• On-board power regulators for all necessary voltages with power status LEDs
• Two types of external power supply jacks (12V “brick” DIN4 type, PC ATX type)
• USB JTAG configuration port for use with USB A-to-Mini-B cable
• System ACE™ controller with companion CompactFlash socket
• General purpose push buttons switches and LEDs for each FPGA
• VGA 2X5 male debug header for FPGA U2
• USB-to-UART bridge with USB Mini-B pcb connector for FPGA U2
• I2C bus hosting EEPROM, clock sources
• A separate SiTime fixed 200 MHz 2.5V LVDS oscillator wired to each FPGAs global clock inputs
• Six pairs of differential clock input SMA connectors
• Six I2C programmable Silicon Labs Si570 3.3V LVPECL 10 MHz-to-810 MHz oscillators
• Two differential input 8X8 cross-point switches providing 16 selectable differential clock sources
• Three sets of plug and receptacle FCI Airmax 120 pin connectors implementing the Interlaken interconnect protocol
• Three MGTH-to-MGTH (four TX/RX channels each) connections between FPGA U1 and FPGA U2
• One MGTX-to-MGTX (four TX/RX channels) connections between FPGA U1 and FPGA U2
• 9 X 32-Bit DDR3 memory on FPGA U1
• 3 x 16-Bit DDR3, 1x18-Bit DDR2 and 2x36-Bit QDR2 memories on FPGA U2
• Netlogic NL92000 series Network Processor adjunct on FPGA U2