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Xilinx Virtex-7 FPGA VC709 Connectivity Kit

 

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$4,995

Part Number:

DK-V7-VC709-G
DK-V7-VC709-G-J

The Virtex®-7 FPGA VC709 Connectivity Kit is a 40Gb/s platform for high-bandwidth and high-performance applications containing all the necessary hardware, tools and IP to power quickly through your evaluation and development of connectivity systems. This includes a 40Gb/s targeted reference design featuring PCI Express Gen 3, a DMA IP core from Northwest Logic, 10GBase-R, AXI, and a Virtual FIFO memory controller interfacing to an external DDR3 memory. To control and monitor this design, the kit includes a connectivity GUI built on Fedora Live OS which includes all the software drivers. Additionally, this kit contains two fiber optic cables and four transceiver modules leveraged by this design.

What's Included

  • VC709 evaluation board featuring the XC7VX690T-2FFG1761C FPGA
  • Targeted Reference Design featuring DDR3, PCIe® and evaluation DMA
  • Four 10Gb Ethernet transceiver modules and two fiber optic patch cables
  • Full seat Vivado™ Design Suite: Design Edition
    • Device-locked to the Virtex-7 XC7VX690T FPGA
  • Printed Getting Started Guide
  • Cables & Power Supply
  • Additional downloadable content including:
    • Reference Designs, Design Examples, and Demos
    • Board Design Files
    • Extensive Documentation

Jump To...

 VC709 Base Board

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 Key Features

FPGA: Virtex-7 XC7VX690T-2FFG1761C
  • ROHS compliant VC709 kit including the XC7VX690T-2FFG1761C
Configuration
  • Onboard JTAG configuration circuitry to enable configuration over USB
  • BPI Parallel NOR Flash: 32MB (256Mb)
Memory
  • DDR3 SODIMM (qty 2) - each with 4GB up to 933MHz / 1866Mbps
  • BPI Parallel NOR Flash: 32MB (256Mb)
  • IIC EEPROM: 1KB (8Kb)
Communication & Networking
  • 4x SFP/SFP+ cages
  • 10x GTH ports to FMC
  • UART To USB Bridge
  • PCI Express 8-lane edge connector
Expansion Connectors
  • FMC-HPC (Partially Populated) connector
  • GTH Transceivers (x10) , 160 single-ended or 80 differential (34 LA & 46 HA) user defined signals
  • VADJ fixed at 1.8 volts
Clocking
  • Fixed Oscillator with differential 200MHz output
    • Used as the “system” clock for the FPGA
  • Fixed Oscillator with differential 233.33MHz output
    • Used as the "memory" clock
  • User Programmable (IIC) Differential Oscillator (Range: 10MHz - 810 MHz, 156.250 MHz default)
  • Differential SMA clock input
  • Differential SMA GTH reference clock input
  • Jitter attenuated clock
    • Used to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module
Control & I/O
  • User Push Buttons (x5)
  • User DIP Switch (8-position)
  • User LEDs (x8)
Power
  • AC Power adapter (12V) or ATX

 Connectivity Peripherals

 Key Features

  • Transceiver Modules (qty 4)
    • Four 10Gb Ethernet transceiver modules compliant with the 10GBASE-SR standard
  • Optical Cable (qty 2)
    • Two Multimode fiber optic patch cables
  • Xilinx offers a 90-day limited warranty on this product. See Limited Warranty for detailed information.

NameDescriptionLicense Type
Vivado Design Suite: Design EditionThe Xilinx Vivado™ Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for all programmable devices.Device locked to the Virtex-7 690T FPGA
Fedora LiveFedora is a fast, stable, and powerful linux-based operating system. The Live version boots to the OS directly from the DVD so users don't have to erase anything on the current system to try it out.V16
PCI Express DMA Engine (from Northwest Logic)PCI Express DMA Engine from Northwest Logic.Eval Version - 12 Hour Hardware Timeout
Memory Interface Generator (MIG)MIG is a free software tool used to generate memory controllers and interfaces for Xilinx FPGAs.No-Charge IP
AXI InterconnectThe AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from ARM®, including the AXI4-Lite control register interface subset.No-Charge IP
AXI Virtual FIFO ControllerThe AXI Virtual FIFO Controller is a key Interconnect Infrastructure IP which enables users to access external memory segments as multiple FIFO blocks. The AXI Virtual Controller provides AMBA® AXI4-Stream write (master) as well as read (slave) interface to AXI4 DRAM memory mapped interface of external memory.No-Charge IP
10 Gigabit Ethernet Media Access Controller (10GEMAC)Xilinx provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system.Eval Version - Simulation Only
10 Gigabit Ethernet PCS/PMA (10GBASE-R)The 10 Gigabit Ethernet PCS/PMA (10GBASE-R) is a no charge Xilinx LogiCORE which provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10.3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification. This optical module can be connect to a 10GBASE-SR, -LR or –ER optical link.No-Charge IP

Featured Design: Virtex-7 Connectivity Targeted Reference Design

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ResourcesDescription
Latest Documents and Design FilesDocumentation and Design Files for the Virtex-7 FPGA VC709 Connectivity Kit.
Master Answer RecordThe latest information answer records for the VC709
Solution CenterAvailable to address all questions related to Xilinx Boards and Kits



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