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FMC XM105 Debug Card

 

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$159


Lead Time : 2 Weeks

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  • Part Number:

    HW-FMC-XM105-G

    Accelerate Your Designs - Right Out of the Box

    Documentation

    Device Family Support

    • Virtex-6
    • Spartan-6

    The FMC XM105 Debug Card is designed to provide access to many of the pins on the FMC connector found on Xilinx FMC-supported boards including the SP601,SP605 and ML605.

    The FMC XM105 Debug Card provides a number of multi-position headers and connectors which break out FPGA interface signals to and from the board interface. A serial IIC bus re-programmable LVDS clock source and a pair of SMA connectors provide differential clock sources to the FMC-supported board FGPA. A 2 Kb serial IIC EEPROM provides non-volatile storage.

    Low pin count (LPC) and high pin count (HPC) FMC board connector interfaces are supported. SP601 and SP605 boards provide a single FMC LPC interface. ML605 provides one FMC LPC and one FMC HPC interface. The FMC XM105 Debug Card contains a FMC HPC connector which mates with LPC or HPC FMC-supported board connectors.

    What's Included

    • FMC XM105 Debug Card
    • Welcome letter
    • Four (4) mounting screws
    • Two (2) standoffs
      Board documentation, schematics, and PCB design files are available.
    • Necessary equipment
      • Small Phillips screwdriver to secure the FMC debug board to the carrier board
      • PC with Internet access to download documentation, board files, and schematics

    Key Features

    • VITA 57.1 FMC HPC connector
      • Single-ended signals from the carrier board, clocks, JTAG, power.
    • 40 Single Ended I/O (20 Pairs) on the LPC Pins
    • 80 Single Ended I/O (40 Pairs) on the HPC Pins
    • Mictor connector 38 pin female Mictor connector
      • Shared I/O with LPC Pins
      • Mictor JTAG pins broken out
    • 16 and 12 additional LPC Single Ended I/O
      • 8 LPC I/O on 6 pin x 2 row male header (2x6 Pmod Header)
      • 4 LPC I/O on 6 pin x 1 row male header (1x6 Pmod Header)
      • Four User LEDS Shared with I/O
    • 12 additional HPC Single Ended I/O
    • FMC JTAG 9-pin header
      • 9 pin x 1 row male header with FMC JTAG connections
    • Clocking
      • SMA connectors
      • Silicon Labs Si570 IIC serial bus re programmable LVDS clock source EEPROM
      • 2 Kb EEPROM, IIC compatible electrically erasable programmable memory (EEPROM) with 2 Kb (256 bytes) of non-volatile storage.
    • Power Good LEDS
      • Power good LEDS for +12V, carrier to mezzanine (PG_C2M) and Vadjust/3.3V
     
     
     
     
     
     
     
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