ML300 Reference Design FAQs

• Reference Design Hardware
• Reference Design Software
• Reference Design Simulation
• Reference Design Other

Reference Design Hardware :

Q. After EDK download, the device goes DONE but nothing happens

A. The EDK download loads a bitstream that has the design + an infinite loop. Your software must be downloaded separately using XMD/GDB. The EDK Download feature has been modified to download the pre-software bitstream. This customization is done in projects/ml300_edk2/etc/download.cmd. The BRAM in this bitstream has been pre-loaded to contain a loop instruction at the PowerPC405 reset vector 0xFFFFFFFC. The purpose of doing this is to prevent the PPC405 from starting to execute immediately after the FPGA wakes up. That situation causes problems when the software does not reside completely within BRAM (if it is also in the PPC405 cache or external DDR memory). These other memories are loaded some time afterwards and your application may access those uninitialized memories beforehand causing catastrophic failure.

Q. The design during place & route does not meet timing, what can I do?

A. The reference design is a very full design. The files have been set up so that unmodified, it should successfully place and route with no timing errors using the specific design tool versions EDK 6.2 and ISE 6.2. (Note: if you have certain core licenses, timing may fail with the unmodified reference design.) If you have timing problems, you may need to adjust the ISE placer cost table. The cost table can be changed in the file projects/ml300_edk3/etc/fast_runtime.opt. Under the par section, it is the "-t" option. The option can take a numerical argument from 1 to 100. Try several different values to see whether one will meet timing.

Q. I loaded the design onto the ML300 Hardware Platform and am trying to communicate via the UART. However, my terminal is not accepting input or is otherwise not behaving correctly. What is wrong?

A. Check your UART terminal settings. The UART terminal must have "Flow control" set to "none". The other settings should be 9600 bits per second, 8 data bits, 1 stop bit, no parity.

Reference Design Software:

Q. In xrom_ml300, how do I know when the LED test is finished?

A. The LED test in xrom_ml300 runs continously until you press either ESCAPE or TAB to exit the test. The message saying this unfortunately does not appear until after you press one of these keys.

Reference Design Simulation

Q. What are the following files in the projects/ml300_edk3/data directory: pci_lc_i.v

A. These simulation verilog netlists are used to workaround a problem generating the simulation netlist for EDK cores that use BBD netlists. For more details, see Xilinx Answer Record 18484.

Reference Design Other:

Q. Is there anything to be careful about when switching between different projects?

A. When switching to a different project (.xmp file), a software clean within XPS to clear the EDK caches and refresh various file dependencies.