ML403 Evaluation Platform Demos and Reference Designs

Getting Started with ML403 Demonstrations

Your ML403 Evaluation Platform is shipped with a number of demonstration designs pre-installed on the CompactFlash card, Platform Flash, and Linear Flash memories. The ML403 Getting Started Tutorial describes how to quickly get started using your ML403. This tutorial also contains a number of hands-on user lab exercises to help you learn to use your ML403. Please download the lab resource files here.

ML403 Image Files for XAPP7171

The ML403 board is used as the demonstration platform for XAPP717: Accelerated System Performance with the APU and XtremeDSP™ modules.
Click here for the IDCT demo sample image.
Click here for the CompactFlash image for the IDCT demo and image data.

ML403 EDK Processor Reference Design

The ML403 example reference systems use the Embedded Development Kit. An IBM CoreConnect™ infrastructure connects the MicroBlaze or PowerPC CPU to numerous peripherals using Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), and Device Control Register (DCR) buses to build a complete system. Each reference system contains hardware and software designs. Please refer to the reference design user guide documentation before proceeding with the design:

EDK 8.1 SP1 / ISE 8.1 SP2
ML403 EDK Processor Reference Design User Guide (PDF)
ML403 EDK Embedded MicroBlaze™ Reference Design (ZIP)
ML403 EDK Embedded PowerPC® Reference Design
Reference Design Archive

ML403 MIG 1.6 DDR SDRAM Interface Reference Design with Chipscope Demonstration

The ML403 board features two Infineon HYB25D256160BT-7 (or compatible) DDR SDRAM memory devices. Each chip is 16 bits wide and together form a 32-bit data bus capable of running up to 266 Mbps/pin. This reference design, available here, provides a memory controller generated using MIG 1.6 (Memory Interface Generator - http://www.xilinx.com/memory). It also features a Chipscope™ demonstration with which data and other signals can be monitored.

ML403 CPLD Reference Design

The ML403 board contains a CPLD that can read the contents of Flash memory and program the FPGA. This demonstrates an alternative method of programming Xilinx FPGAs. The CPLD also supports the ability to load one of eight possible bitstream revisions depending on the Configuration Address DIP Switch settings. Click here for the ML403 CPLD Reference Design which includes source files and information on how to rebuild the design.

ML403 DSP48 Video Demonstration

The ML403 Evaluation Platform includes a USB keyboard demonstration design on the Compact Flash card. Click here for documentation and source files for the USB demonstration design.

ML403 USB Demonstration Design

The ML403 Evaluation Platform includes a USB keyboard demonstration design on the Compact Flash card. Click here for documentation and source files for the USB demonstration design.

Restoring ML403 Demonstration Images

The files below can be used to restore the CF card, Platform Flash, CPLD, and Linear Flash devices to their default images:

The ML403 Compact Flash (CF) contains a DOS FAT16 file system partition and a Linux EXT3 file system partition. The DOS file system's directory structure is consistent with the requirements of Xilinx' System ACE CF controller, used to load designs on the ML403.

CF Card Image (DOS Partition) (ZIP)
CF Card Image (DOS and Linux Partition) (ZIP) (174MB)

Click here for instructions and tools for re-imaging your CF card that can be applied to ML403. Caution: Read and follow instructions very carefully!
Use XCSC tool to calculate Checksums.

Platform Flash Image (ZIP)
CPLD Image (ZIP)

Linear Flash Image: use program 7 on the CF card to re-program the linear flash

 
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