| EDK 8.1 / ISE 8.1 |
|
 |
| ML405 |
- Virtex-4 Silicon Errata
View Virtex™-4 Silicon Errata
- TX_Disable input to SFP module
AR 31703 - TX_Disable input to SFP module can be driven to undefined state
- Ethernet PHY Address Setting
AR 23948: Identifying the ML405 Ethernet PHY Address Setting
- MGT LVDS Clock Frequencies
The ML405 has a 125 MHz SGMII clock and a 150 MHz SATA clock to the MGTs. This clock frequency is below the 156 MHz clock frequency described in the errata leading to potentially increased transceiver jitter. If a 250 MHz SGMII clock is desired, replace X14 with a 20 MHz crystal and replace U52 with ICS844031AGI-01 from ICST.
Note: Xilinx is not responsible for boards damaged by users attempting to solder on different parts.
- Treck Web Server Demo
The Treck Web Server demo pre-installed on the CF card (at \ml405\webserve\ml405_treck.ace) may fail to establish an Ethernet link. An updated image is available for download here. You can determine if your ML405 already has the updated demo file by opening the README.TXT file on the CF Card. If it says “VERSION 2”, then it includes the updated demo.
- Encryption Key Battery Installed Backwards
On some ML405 boards, the encryption key battery (Reference Designator "B1") may be installed backwards. In order for the encryption keys to be held in the FPGA during power off, it is necessary to install the battery such that the “+” terminal faces up. Therefore the (+) terminal of the battery should be facing up to contact the (+) terminal of the socket. Note: diodes on the board block the FPGA from seeing any reverse battery voltage.
|
|
|
|
