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ML40x Known Issues

EDK 8.1 / ISE 8.1
1) Encryption Key Battery Socket Polarity Reversed
On ML401, ML402, and ML403 boards, the encryption key battery socket (Reference Designator “B1”) has its polarity reversed. In order for the encryption keys to be held in the FPGA during power off, it is necessary to install a smaller CR1025 lithium battery upside down from what is marked on the socket. Therefore the (-) terminal of the battery should be facing up to contact the (+) terminal of the socket. Note: diodes on the board block the FPGA from seeing a reverse battery voltage.
2) ADV7125 Ground Pins
On ML401, ML402, and ML403 boards, some of the ground pins of the Video DAC (ADV7125 - U13) are connected to digital ground instead of analog ground resulting in increased VGA video noise. Ground pins 1, 2, 14, 15, 39, and 40 of U13 should be connected to the analog ground (Pin 2 of FB6).
3) Using XMD/ChipScope on ML401 Boards with LX25 ES Devices
On ML401 Boards with LX25 ES silicon, users may experience problems connecting to the board using XMD or ChipScope™ due to a silicon errata. Please refer to Answer Record 20060 for important information on using XMD and ChipScope with ML401 Boards containing LX25 ES devices. Please note that the ML401 Embedded MicroBlaze Reference Design is already preconfigured to have the XMD workaround in place.
4) Virtex-4 Silicon Errata
View Virtex™-4 Silicon Errata
5) PowerPC Startup Issue (ML403)
If you experience issues where the PowerPC® processor does not boot on power up, please refer to Answer Record 22179 for more information. The ML403 EDK Embedded PowerPC Reference Design and Demonstration Image Files have been updated to include the new C_APU_CONTROL setting. If any of your pre-installed ML403 CompactFlash, Platform Flash, or Linear Flash images do not boot properly, it may be necessary to update your Flash image files. You can determine if your ML403 already has the updated flash images by opening the README.TXT file on the CF Card. If it says "CONTENT VERSION 3" then it includes the updated C_APU_CONTROL setting.
6) Intermittent FPGA Programming By CPLD Upon Startup
In CPLD + Linear Flash configuration mode, the CPLD reference design may intermittently fail to configure the FPGA upon power-up. (The FPGA always programs successfully after the PROG button is pressed). The issue has been identified and corrected. The CPLD reference design source files and .jed programming files have been updated on the ML40X Reference Design web pages.

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