******************************************************************************* * * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * * (c) Copyright 2004 Xilinx, Inc. * All rights reserved. * ******************************************************************************/ /******************************************************************************/ WARNING! Read documentation BEFORE using 3.3V PCI slots. Please see the PCI section below. /******************************************************************************/ ============ ML410 Readme ============ Tools ===== All ML410 reference designs were built with the following tools: Xilinx Implementation Tools: ISE 8.2i SP2 (I.33) EDK 8.2i SP1 (Im_Sp1.3) Answer Records ============= AR# 20232 - PowerPC405 CCR0 Usage of the Core-Configuration Register and Reset AR# 20658 - CCR0 (PPC405 IBM Errata) Download the errata pdf and look for note CPU_213: ftp://ftp.xilinx.com/pub/documentation/misc/ppc405f6v5_2_0.pdf To implement these two Answer Records (20232 & 20658), set CCR0 to 0x50700000 when using XMD to manually download Linux. The included ACE creation script (genace.tcl) already does this. AR# 19774 - TIG PPC Resets (BSB) AR# 21127 - MGT: New DCM parameters for Virtex-4 AR# 23410 - MGT: Using a Null Tile PCore for MGTs AR# 24004 - Setting the TestApp PHY Address All reference designs included with the ML410 documentation already have implemented the Answer Records listed above. NOTE: All Answer Records are accessible via http://support.xilinx.com ML410 CompactFlash ================= This Compact Flash (CF) contains a DOS FAT16 filesystem partition and a Linux EXT3 filesystem partition. The DOS filesystem's directory structure is consistent with the requirements of Xilinx' System ACE CF controller, used to bring-up and launch applications on the ML410. QuickStart ========== 0. Warning! Read documentation before using 3.3V PCI slots. Please see the PCI section below. 1. Connect the ML410 (192.168.0.2) to a PC Host (192.168.0.1) with a private network connection using either a cross-over cable, Ethernet switch, or Ethernet hub. 2. Connect a Null modem cable between the ML410 COM0 RS232 port and a PC host running a terminal program such as TeraTerm or HyperTerminal set for 9600 baud, 8 bits, No parity, 1 stop bit, and no hardware flow control. (9600, 8-N-1, no HW flow control) 3. Set DIP Switch SW3 to boot the ACE-loader located in configuration 0. All switches towards ON and the DIP switch numbers. 4. Insert CF into the CF slot J22, located near the System ACE CF ASIC (U38). 5. The following demonstration programs are on the CompactFlash: cf0 -> ace_loader.ace cf1 -> ml410_pci_linux.ace cf2 -> ml410_bsb_vxworks.ace cf3 -> cf4 -> ml410_bsb_bootloop.ace cf5 -> ml410_bsb_vxworks_sw.ace cf6 -> cf7 -> 6. Turn power on or press and release SW1, the SYSACE RESET pushbutton. 7. The ML410 Diagnostics/ACE-loader menu similar to the one below will appear. Select the desired application as noted above. ML410 ACE-loader ---------------- Enter Desired System ACE CF Configuration <0-7>. 0: ACE-loader. 1: Configuration 1. 2: Configuration 2 3: Configuration 3 4: Configuration 4 5: Configuration 5 6: Configuration 6 7: Configuration 7 Select <0-7>: Applications ============ These are brief descriptions of the demonstrations available on the CompactFlash. Please see the ML410 documentation for detailed and highly visual How-To Powerpoint presentations. Config 0: ACE-loader menu is presented to launch additional applications. Config 1: Monta Vista Embedded Linux console login. Connect the ML410 (192.168.0.2) to a PC Host (192.168.0.1) with a private network connection using either a cross-over cable, Ethernet switch, or Ethernet hub. Login as root with the following login and password: ml410 login: root Password: 410ml To enable Linux networking and set the ML410 IP address at the Linux root prompt (root@ml410:~#) enter: root@ml410:~# ifconfig eth0 192.168.0.2 netmask 255.255.255.0 Network statistics are available with: root@ml410:~# ifconfig From a PC Host that has been set up with an IP address of 192.168.0.1 open a command window to ping the ML410. (Start->Run, then enter: cmd, select OK) Ping the ML410 using: ping 192.168.0.2 Linux uses the ext3 filesystem on the CF, therefore a shutdown must be done before leaving the Linux application to avoid filesystem corruption. Issue the command below from a root prompt halt the system. root@ml410:~# shutdown -h now It is safe to change applications once the System Halted message is seen on the console window. Config 2: VxWorks 5.5 with Networking. Target shell and WDB agent for Tornado 2.2.1 tools connectivity are built into the system image. Enter commands at the Target shell prompt (->) to interact with the VxWorks 5.5 system image. The 'i' command lists the running VxWorks tasks: -> i The CF can be mounted as a local filesystem using the command: -> sysSystemAceMount(0,"/cf0",1) The files on the Compact Flash disk can now be viewed using these commands: -> cd "cf0" -> ll Networks statistics are available with: -> ifShow From a PC Host that has been set up with an IP address of 192.168.0.1 open a command window (Start->Run, then enter: cmd, select OK) Ping the ML410 using: ping 192.168.0.2 Ping from the ML410 to the PC Host (quotes required here): -> ping "192.168.0.1" Enter Ctrl-C to stop the ping program. Config 4: ml410_bsb_bootloop.ace Xilinx Platform Studio (XPS) Base System Builder (BSB) generated design with bootloop code in block RAM. Config 5: ml410_bsb_vxworks_sw.ace Software only ACE file containing a VxWorks image that can be loaded after configuring the FPGA with the ml410_bsb_bootloop.ace file. System ACE Compact Flash (FAT16 Partition) ========================================= Each cf# directory on the Compact Flash contains the ".bit" and "elf" file used to created the ".ace" file. The SystemACE CF only requires a single ".ace" file in each cf# subdirectory, the ".bit" and "elf" are for convenience purposes and can deleted to free up space. The ML410 CDROM contains a duplicate 512MB "dd" image of the CF disk shipped with the ML410. Instructions on CF re-imaging are provided with the ML410 documentation. G:. | xilinx.sys | vxWorks | ml410_readme.txt | \---xilinx +---cf0 | ace_loader.ace | +---cf1 | ml410_pci_linux.ace | +---cf2 | ml410_bsb_vxworks.ace | +---cf3 +---cf4 | ml410_bsb_bootloop.ace | +---cf5 | ml410_bsb_vxworks_sw.ace | +---cf6 \---cf7 PCI === The ML410 board is PCI 2.3 compliant. Note Section 4.4.1 of the PCI 2.3 spec states: 4.4.1. Add-in Card Pin Assignment Pins labeled "+VI/O" are special power pins for defining and driving the PCI signaling rail on the Universal add-in card. On this add-in card, the PCI component's I/O buffers must be powered from these special power pins only not from the other +3.3V or +5V power pins. ++++++ WARNING ++++++ WARNING: Some Universal add-in cards are non-compliant with PCI 2.3, they violate Section 4.4.1. and are "broken" by design. Due to design legacy from earlier 5V systems, some Universal PCI cards have VI/O directly connected to the 5V supply voltage. This is non-compliant with PCI 2.3, Section 4.4.1. A universal PCI card that is non-compliant with PCI 2.3 plugged into a 3.3V PCI compliant slot will result in the short circuit of the 3.3V and 5V supply voltages. Xilinx is not responsible for damage due to connecting add-in cards that are non-compliant with PCI 2.3 Section 4.4.1. It is the user's responsibility to ensure add-in cards are PCI 2.3 compliant. It is the user's responsibility to perform a continuity check between VI/O and 5V power pins prior to inserting an add-in card into an ML410 3.3V PCI slot. Any cards that have a short between (VI/O and 5V) or (VI/O and 3.3V) power pins are non-compliant with Section 4.4.1 of the PCI 2.3 specification and are NOT be used. Prior to plugging in a universal card, an ohmmeter should be used to determine if the VI/O is shorted to either the 5V or 3.3V pins on the card. For example, a continuity check between VI/O pin B19 and 5V pin B5 must NOT present a short-circuit. The VI/O, 5V and 3.3V pins exist on a PCI card's edge connector on the pins specified in the tables below. The Bxx numbers refer to the component side of the card, whereas the Axx numbers refer to the opposite (solder) side. Partial PCI Edge Connector Layout COMPONENT SIDE (B) +--LEFT EDGE | v | | | | | | | | | | | | | | | | | | | | | | | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 * * * * * * (5V) (3.3V Key) (Vio) (3.3V) Universal (32-bit) PCI Add-in Card Pin Locations +VI/O PINS +5V PINS ----------- ---------------- Component Side: B19, B59 B5, B6, B61, B62 Opposite Side: A10, A16, A59 A5, A8, A61, A62 +3.3V PINS ---------------------------- Component Side: B25, B32, B36, B41, B43, B54 Opposite Side: A21, A27, A33, A39, A45, A53 +3.3V KEY +5V KEY -------- -------- Component Side: B12, B13 B50, B51 Opposite Side: A12, A13 A50, A51 Universal Add-in Card Pin Side B Side A Comments 1 32-bit start 2 3 4 5 +5V +5V 6 +5V 7 8 +5V 9 10 +VI/O 11 12 KEYWAY 3.3V key 13 KEYWAY 3.3V key 14 15 16 +VI/O 17 18 19 +VI/O 20 21 +3.3V 22 23 24 25 +3.3V 26 27 +3.3V 28 29 30 31 +3.3V 32 33 +3.3V 34 35 36 +3.3V 37 38 39 +3.3V 40 41 +3.3V 42 43 +3.3V 44 45 +3.3V 46 47 48 49 50 KEYWAY 5V key 51 KEYWAY 5V key 52 53 +3.3V 54 +3.3V 55 56 57 58 59 +VI/O +VI/O 60 61 +5V +5V 62 +5V +5V 32-bit end