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S$1@1 a0! 0!(a $,!0e@C<08H<00``@a $(,!00!43!@2 `|2sS23XӾ22 W$011 ߸l08H00``@T0!08H 0d@C$0H0``@0! $@0!0!a $ge@C008H00``@a $0!("@FR\@"@GRd"@wF$2g "@S$2s"@SRv08HH00``@p08H000``@X08H00``@@0!e@C$08H00``@0!"@FR,@"@GR<@0!08H00``@0!08Hl00``@08HT00``@t0!a!, $(A0a48<@D%fe@CP08H0o0``@a $(!,A0a48<@D0!HS S 0py@y $C(08HT00``@y0cy`"@^R@"@_R"@S` 0`9xD@~2Vx2R2cc2s2# PV23\ 23ZH0 08Ht0n0``@X|08HL00``@08H400``@08H00``@0!fa $0\F1@x1 c 0`0e e $@a $`0!(08HT0]0``@08H<0``@`?x0?xEd0!ae:e( $ e#0eH$ 1)eH 1)`H5CeH1J*1)`:0!A0a4a $(!,HePFx82cS<`0dt wC2s2S22a $(!,A0a40!882s2S2x0cCԾl0yS2R2 dDyd#82s2sSH2sS22s482sd2x|x0cChLy0S2R2 d$yd#082s82s2x82s20!0`33 E0E00eFp E0d 0`2@ƐHf(E(3(c_ `33 ܸ`0! 0!|33 E0p0`E0`F\ F(RP H0`E(3( _ 0c3 cܸ`0! `50!a2`5C2ssC2a0! 0!x0!0!0!Design #0 LoadedThis is flash configuration 0The FPGA has been configured from the Linear Flash memory (BPI Mode) The FPGA has been configured from the Linear Flash memory (BPI Mode) This is flash configuration %d On the reference design, this bit file is at memory location 0x%08X Using Flash0123456789ABCDEFLTTTTTTT`pTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTxTTTTTTTTTTTTT TTTTTT TTTT!xtft.c ((((( AAAAAABBBBBB ((((( AAAAAABBBBBB ?C5"X((HHHHHH|||* P@@`b @@@ T88T| @@8DD8088D @~BBBBF:@@@|BBBB|BBBF:8@@XdBBBBB`DHP``PHDlXdDDDDD8DD8||Xd@@@@@8@@8D88 DDDDDL4DDDD(lD((DBBF:<| @| @   ` @@9?:% $ > $ >  I: ; I: ;I : ;  : ; I8 .? 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