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This ** limitation shall apply notwithstanding the failure of the ** essential purpose of any limited remedies herein. ** ******************************************************************************* Application: flash_hello ------------------------- We will configure the FPGA, download code, and view the resulting output. The flash_hello application is meant to reside in the linear flash memory device and be used with the new Byte Peripheral Interface (BPI) configuration mode of the Virtex-5. However, before programming the linear flash with this application, we will test it by initializing the instruction and data memories with a download cable. Once satisfied with the behavior of the program, we will program the linear flash with the application and re-check its behavior. Note: Please see the Virtex-5 Configuration User Guide (UG191) for more details on the new Virtex-5 configuration modes. CONFIG Switch Settings: 00010101 1. Connect the Host PC to the ML501 (J1 header) using a PC-IV or Platform USB JTAG cable 2. Connect the Host PC serial port to the ML501 serial port using a null modem cable and launch a terminal program on the Host (eg. TeraTerm) with the settings: 9600 baud, 8-N-1, No flow control 3. Connect the ML501 to a DVI monitor or to a VGA monitor with the appropriate adapter 4. Launch XPS and open the ML501 EDK project (system.xmp) 5. Launch a Shell window using XPS menu selection: Project > Launch EDK Shell 6. Download bitstream in shell window by typing: impact -batch etc/download.cmd 7. XPS menu selection: Debug > Launch XMD 8. At XMD% prompt type: cd microblaze_0/code 9. At XMD% prompt type: rst 10. At XMD% prompt type: dow flash_hello.elf 11. At XMD% prompt type: con 12. We have just configured and downloaded the flash_hello application using the JTAG cable. The resulting output is shown below. LCD Output: ----------- Design #0 Loaded Using Flash Serial Port Output: ------------------- The FPGA has been configured from the Linear Flash memory (BPI Mode) This is flash configuration 0 On the reference design, this bit file is at memory location 0x28000000 DVI/VGA Output: --------------- The FPGA has been configured from the Linear Flash memory (BPI Mode) This is flash configuration 0 ****************************************************************************** The jtagflasher.exe utility can be used to program the ML501 linear flash. ****************************************************************************** 1. We will assume the jtagflasher.zip has been extracted into some directory, hereafter referred to as 2. Open a DOS command shell 3. cd 4. Copy the bit file destined for the linear flash to copy \.bit . 5. Create a BIN file. This will be used to program the linear flash device promgen -w -p bin -o .bin -u 0 .bit 6. Program the linear flash at a specific configuration location by selecting and entering the appropriate jtagflasher command and its arguments from the choices below: configuration 0: jtagflasher -b 10 0 .bin configuration 1: jtagflasher -b 10 0x800000 .bin configuration 2: jtagflasher -b 10 0x1000000 .bin configuration 3: jtagflasher -b 10 0x1800000 .bin For example, enter: jtagflasher -b 10 0 flash_hello.bin 7. Select and set the CONFIG DIP switch values to indicate the desired linear flash configuration location: configuration 0: 00001001 configuration 1: 00101001 configuration 2: 01001001 configuration 3: 01101001 For example, to use configuration 0, set CONFIG Switch Settings: 00001001 8. Press the PROG pushbutton to configure the Virtex-5 from the linear flash using the configuration selected above 9. The resulting output of configuring the Virtex-5 using the linear flash should match the initialization via download cable results shown earlier.