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Virtex-5 ML505 Evaluation & Development Platform
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ML505 Reference Designs
: ML505 Aurora Reference Designs
Xilinx ML505 Aurora Reference Designs
Product Details
ML505 GTP Aurora Design
This reference design and tutorial demonstrates a 2 byte, single lane GTP Aurora design
ML505 GTP Aurora
ml505_vlog_aurora_201.zip
ML505 GTP Aurora Design with CRC Addition
This reference design and tutorial demonstrates a 2 byte, single lane GTP Aurora design with CRC32 hard macro
ML505 GTP Aurora with CRC Addition
ml505_vlog_crc_aurora_201.zip
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Previous Aurora Revision
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Virtex®-5 FPGAs
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