The Integrated Bit Error Ratio Tester (IBERT) designs provide users access to the Virtex-5 RocketIO™ GTP transceivers. The IBERT core contains pattern generators and checkers that exercise the high-speed serial GTP transceivers. In addition, each RocketIO transceiver’s attributes can be accessed through the IBERT console.
IBERT design creation and verification using loopback and test equipment available from third-party vendors. This IBERT design includes GTP transceivers associated with the SATA, SGMII, SMA, SFP, PCIe, and onboard loopback interfaces.
ML505 4GTPs IBERT QuickStart (PDF)