Xilinx ML505 Aurora Reference Designs

ML505 GTP Aurora Design

This reference design and tutorial demonstrates a 2 byte, single lane GTP Aurora design

ML505 GTP Aurora (PDF)
ml505_vlog_aurora_201.zip (ZIP)

ML505 GTP Aurora Design with CRC Addition

This reference design and tutorial demonstrates a 2 byte, single lane GTP Aurora design with CRC32 hard macro

ML505 GTP Aurora with CRC Addition (PDF)
ml505_vlog_crc_aurora_201.zip (ZIP)