The Integrated Bit Error Ratio Tester (IBERT) designs provide users access to the Virtex-5 RocketIO™ GTP transceivers. The IBERT core contains pattern generators and checkers that exercise the high-speed serial GTP transceivers. In addition, each RocketIO transceiver’s attributes can be accessed through the IBERT console.
IBERT design creation and verification of the SATA GTP transceivers using the included SATA cross-over cable.
ML505 IBERT QuickStart (PDF)IBERT design creation and verification using loopback and test equipment available from third-party vendors. This IBERT design includes GTP transceivers associated with the SGMII, SMA, SFP, PCIe, and onboard loopback interfaces.
ML505 3GTPs IBERT QuickStart (PDF)