Xilinx ML506 PCIe x1 Endpoint Designs

ML506 PCIe x1 Endpoint Plus Design

The Xilinx CORE Generator is used to create a single-lane PCIe Endpoint Plus design. The generated PCIe system contains the PCIe endpoint plus block, GTP tiles, block RAMs, and clock and reset modules. The tutorial below shows how to create the PCIe design with the PCIe Wizard and how to verify its functionality.